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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 16-bit single-chip microcomputer 7700 family / 7900 series user s manual 7906 group before using this material, please visit the above website to confirm that this is the most current document available. http://www.infomicom.maec.co.jp/indexe.htm rev. 2.0 revision date: dec. 20, 2001
keep safety first in your circuit designs! notes regarding these materials mitsubishi electric corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semicon- ductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or repro- duce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
revision history 7906 group user? manual rev. date description page summary (1/1) 1.0 07/04/01 1.1 08/03/01 2.0 12/03/01 1-5 2-8 3-3 5-6 6-18 7-15 7-16 7-26 8-6 8-7 8-10 8-16 9-4 9-5 9-6 9-13 10-3 10-14 10-16 10-17 11-17 11-18 11-19 11-35 12-2 12-5 12-7 12-11 12-19 12-20 12-22 12-23 12-25 12-26 12-28 12-29 13-3 17-6 17-10 17-11 19-20 20-28 20-35 20-110 20-113 20-116 20-119 first edition a blank page is inserted before chapter 1. table 1.3.1 line 3 figure 3.1.2 line 6 line 8 line 10 line 5 line 7 line 2 figure 8.2.6 figure 8.3.2 figure 8.4.3 figure 9.2.2 table 9.2.2 line 2 line 18 figure 10.1.1 figure 10.2.12 figure 10.2.15 table 10.3.1 and line 6 lines 9 and 13 figure 11.2.14 note 1 in figure 11.2.1 line 26 table 12.1.1 note 5 in figure 12.2.2 line 30 figure 12.2.8 figure 12.7.1 figure 12.7.2 figure 12.8.1 figure 12.8.2 figure 12.9.1 figure 12.9.2 figure 12.10.1 figure 12.10.2 line 13 figure 17.3.1 figure 17.4.1 figure 17.4.2 table 19.3.1 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) note 1 in d-a control register (address 93 16 ) dc electrical characteristics timer a input : test conditions external clock input i cc ?(x in ) standard characteristics a blank page is inserted after the end of appendix 11.
this manual describes the hardware of the mitsubishi cmos 16-bit microcomputers 7906 group. after reading this manual, the user will be able to understand the functions, so that they can utilize their capabilities fully. for details of software, refer to the ?900 series software manual. for details of development support tools, refer to the ?itsubishi microcomputer development support tools homepage ( http://www.tool-spt.maec.co.jp/index_e.htm ). preface
1 before using this manual 1. constitution this user? manual consists of the following chapters. refer to the chapters relevant to the products and processor mode. in this manual, ?37906?means all of or one of the 7906 group products, unless otherwise noted. each chapter, except for chapter 19, describes functions of the 7906 group product at md0 and md1 = vss level. chapter 1. description to chapter 17. debug function functions which are common to all products is described. chapter 18. applications example of application are described. chapter 19. flash memory version characteristics information for the flash memory version is described. appendix practical information for using the 7906 group is described. 2. remark product expansion refer to the latest datasheets or catalogs. electrical characteristics refer to the latest datasheets. software refer to the ?900 series software manual. development support tools refer to the latest datasheets or catalogs. please visit our web site. ?mitsubishi mcu technical information ( http://www.infomicom.maec.co.jp/indexe.htm ) ?mitsubishi microcomputer development support tools ( http://www.tool-spt.maec.co.jp/index_e.htm ) 3. signal levels in figure as a rule, signal levels in each operation example and timing diagram are as follows. ?signal levels the upper line indicates ?,?and the lower line indicates ?. ?input/output levels of pin the upper line indicates ?,?and the lower line indicates ?. foe the exception, the level is shown on the left side of a signal.
2 4. register structure the view of the register structure is described below: xxx register (address xx 16 ) 0 1 2 3 4 5 6 7 ???select bit ???select bit ???flag fix this bit to ?. this bit is invalid in ?mode. nothing is assigned. the value is ??at reading. b7 b6 b5 b4 b3 b2 b1 b0 0 : 1 : 0 : 1 : the value is ??at reading. 0 x 0 0 : 0 1 : 1 0 : 1 1 : b2 b1 ? 1 ? 2 ? 3 ? 5 undefined 0 0 0 0 0 undefined 0 ? 6 wo rw rw ro rw rw ? 0 or 1 according to the usage. 0 : set to 0 at writing. 1 : set to 1 at writing. ? 0 or 1. : nothing is assigned. ? 0 immediately after reset. 1 : 1 immediately after reset. undefined : undefined immediately after reset. ? 0 or 1. wo : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [ 0 at reading ] is indicated in the function or note column, the bit is always 0 at reading. (see ? : it is impossible to read the bit state. the value is undefined at reading. however, when [ 0 at reading ] is indicated in the function or note column, the bit is always 0 at reading. (see ? 0 or 1. ? ?
7906 group user? manual rev.2.0 i table of contents table of contents chapter 1. description 1.1 performance overview .......................................................................................................... 1-2 1.2 pin configuration ................................................................................................................... 1-3 1.3 pin description ....................................................................................................................... 1-5 1.4 block diagram ........................................................................................................................ 1-6 chapter 2. central processing unit (cpu) 2.1 central processing unit (cpu) ........................................................................................... 2-2 2.1.1 accumulator (acc) .......................................................................................................... 2-3 2.1.2 index register x (x) ....................................................................................................... 2-3 2.1.3 index register y (y) ....................................................................................................... 2-3 2.1.4 stack pointer (s) ............................................................................................................ 2-4 2.1.5 program counter (pc) ................................................................................................... 2-5 2.1.6 program bank register (pg) ......................................................................................... 2-5 2.1.7 data bank register (dt) ................................................................................................ 2-5 2.1.8 direct page register 0 to 3 (dpr0 to dpr3) ............................................................ 2-6 2.1.9 processor status register (ps) ..................................................................................... 2-8 2.2 bus interface unit (biu) ..................................................................................................... 2-10 2.2.1 instruction prefetch ...................................................................................................... 2-11 2.2.2 data transfer (read and write) .................................................................................. 2-12 2.3 access space ....................................................................................................................... 2-14 2.4 memory assignment ............................................................................................................ 2-15 2.4.1 memory assignment in internal area ......................................................................... 2-15 2.5 processor modes ................................................................................................................. 2-19 2.5.1 single-chip mode .......................................................................................................... 2-19 2.5.2 setting of processor mode .......................................................................................... 2-20 [precautions for setting of processor mode] ...................................................................... 2-21 chapter 3. reset 3.1 reset operation ...................................................................................................................... 3-2 3.1.1 hardware reset ............................................................................................................... 3-2 3.1.2 software reset ................................................................................................................ 3-3 3.1.3 power-on reset ............................................................................................................... 3-4 3.2 pin state ............................................................................................................................... ... 3-5 3.3 state of internal area ............................................................................................................ 3-6 3.4 internal processing sequence after reset ...................................................................... 3-15 chapter 4. clock generating circuit 4.1 oscillation circuit examples ............................................................................................... 4-2 4.1.1 connection example with resonator/oscillator ............................................................ 4-2 4.1.2 externally generated clock input example .................................................................. 4-2 4.1.3 connection example of filter circuit ............................................................................. 4-3
7906 group user? manual rev.2.0 ii table of contents 4.2 clocks ............................................................................................................................... ....... 4-4 4.2.1 clocks generated in clock generating circuit ............................................................. 4-5 4.2.2 clock control register 0 ................................................................................................. 4-6 4.2.3 particular function select register 0 ............................................................................. 4-9 [precautions for clock generating circuit] ........................................................................... 4-11 chapter 5. input/output pins 5.1 overview ............................................................................................................................... ... 5-2 5.2 programmable i/o ports ....................................................................................................... 5-2 5.2.1 direction register ............................................................................................................ 5-3 5.2.2 port register .................................................................................................................... 5-4 5.2.3 pin p6out cut /int 4 (port-p6-output-cutoff signal input pin) ..................................... 5-6 5.3 examples of handling unused pins .................................................................................. 5-7 chapter 6. interrupts 6.1 overview ............................................................................................................................... ... 6-2 6.2 interrupt sources ................................................................................................................... 6-3 6.3 interrupt control ..................................................................................................................... 6-5 6.3.1 interrupt disable flag (i) ................................................................................................ 6-7 6.3.2 interrupt request bit ....................................................................................................... 6-7 6.3.3 interrupt priority level select bits and processor interrupt priority level (ipl) ...... 6-7 6.4 interrupt priority level .......................................................................................................... 6-9 6.5 interrupt priority level detection circuit ......................................................................... 6-10 6.6 interrupt priority level detection time ............................................................................ 6-12 6.7 sequence from acceptance of interrupt request until execution of interrupt routine ... 6-13 6.7.1 change in ipl at acceptance of interrupt request .................................................. 6-14 6.7.2 push operation for registers ....................................................................................... 6-15 6.8 return from interrupt routine ........................................................................................... 6-16 6.9 multiple interrupts ............................................................................................................... 6-16 6.10 external interrupts ............................................................................................................ 6-18 6.10.1 int i interrupt ............................................................................................................... 6-18 6.10.2 functions of int i interrupt request bit .................................................................... 6-21 6.10.3 switching of int i to interrupt request occurrence factor ...................................... 6-22 [precautions for interrupts] ..................................................................................................... 6-23 chapter 7. timer a 7.1 overview ............................................................................................................................... ... 7-2 7.2 block description .................................................................................................................. 7-4 7.2.1 counter and reload register (timer ai register) ........................................................ 7-5 7.2.2 timer a clock division select register ......................................................................... 7-6 7.2.3 count start register ........................................................................................................ 7-7 7.2.4 timer ai mode register ................................................................................................. 7-8 7.2.5 timer ai interrupt control register ................................................................................ 7-9 7.2.6 port p2 and port p6 direction registers .................................................................... 7-10 7.3 timer mode ........................................................................................................................... 7-11 7.3.1 setting for timer mode ................................................................................................ 7-13 7.3.2 operation in timer mode ............................................................................................. 7-14 7.3.3 select function .............................................................................................................. 7-15
7906 group user? manual rev.2.0 iii table of contents [precautions for timer mode] .................................................................................................. 7-17 7.4 event counter mode ........................................................................................................... 7-18 7.4.1 setting for event counter mode ................................................................................. 7-21 7.4.2 operation in event counter mode .............................................................................. 7-23 7.4.3 switching between countup and countdown ............................................................ 7-24 7.4.4 selectable functions ..................................................................................................... 7-26 [precautions for event counter mode] .................................................................................. 7-28 7.5 one-shot pulse mode ......................................................................................................... 7-29 7.5.1 setting for one-shot pulse mode ............................................................................... 7-31 7.5.2 trigger ........................................................................................................................... 7-33 7.5.3 operation in one-shot pulse mode ............................................................................ 7-35 [precautions for one-shot pulse mode] ................................................................................ 7-37 7.6 pulse width modulation (pwm) mode ............................................................................ 7-38 7.6.1 setting for pwm mode ................................................................................................ 7-40 7.6.2 trigger ........................................................................................................................... 7-42 7.6.3 operation in pwm mode ............................................................................................. 7-43 [precautions for pulse width modulation (pwm) mode] ................................................... 7-47 chapter 8. timer b 8.1 overview ............................................................................................................................... ... 8-2 8.2 block description .................................................................................................................. 8-2 8.2.1 counter and reload register (timer bi register) ........................................................ 8-3 8.2.2 count start register ........................................................................................................ 8-4 8.2.3 timer bi mode register ................................................................................................. 8-4 8.2.4 timer bi interrupt control register ................................................................................ 8-5 8.2.5 port p2 direction register, port p5 direction register ............................................... 8-6 8.2.6 count source (in timer mode and pulse period/pulse width measurement mode) ......... 8-7 8.3 timer mode ............................................................................................................................. 8- 8 8.3.1 setting for timer mode ................................................................................................. 810 8.3.2 operation in timer mode ............................................................................................. 8-11 [precautions for timer mode] .................................................................................................. 8-12 8.4 event counter mode ........................................................................................................... 8-13 8.4.1 count source ................................................................................................................ 8-15 8.4.2 setting for event counter mode ................................................................................. 8-16 8.4.3 operation in event counter mode .............................................................................. 8-17 [precautions for event counter mode] .................................................................................. 8-18 8.5 pulse period/pulse width measurement mode ............................................................. 8-19 8.5.1 setting for pulse period/pulse width measurement mode ...................................... 8-22 8.5.2 operation in pulse period/pulse width measurement mode ................................... 8-23 [precautions for pulse period/pulse width measurement mode] .................................... 8-29 chapter 9. pulse output port mode 9.1 overview ............................................................................................................................... ... 9-2 9.2 block description .................................................................................................................. 9-3 9.2.1 waveform output mode register ................................................................................... 9-4 9.2.2 three-phase output data registers 0, 1 ...................................................................... 9-6 9.2.3 port p2 direction register, port p7 direction register ............................................... 9-9 9.2.4. timers a0 to a4 .......................................................................................................... 9-11 9.2.5. pin p6out cut (pluse-output-cutoff signal input pin) .............................................. 9-13
7906 group user? manual rev.2.0 iv table of contents 9.3 setting of pulse output port mode ................................................................................. 9-14 9.4 pulse output port mode operation .................................................................................. 9-19 9.4.1 pulse output trigger ..................................................................................................... 9-19 9.4.2 operation at internal trigger ....................................................................................... 9-20 9.4.3 operation at external trigger ...................................................................................... 9-23 [precautions for pulse output mode] .................................................................................... 9-24 chapter 10. therr-phase waveform mode 10.1 overview .............................................................................................................................. 1 0-2 10.2 block description .............................................................................................................. 10-4 10.2.1 waveform output mode register ............................................................................... 10-5 10.2.2 dead-time timer register ........................................................................................... 10-7 10.2.3 three-phase output data register 0 ......................................................................... 10-9 10.2.4 three-phase output data register 1 ....................................................................... 10-10 10.2.5 position-data-retain function control register ........................................................ 10-12 10.2.6 port p5 direction register ........................................................................................... 10-13 10.2.7 timers a0 through a2 ............................................................................................. 10-13 10.2.8 timer a3 .................................................................................................................... 10-14 10.2.9 output polarity set toggle flip-flop ......................................................................... 10-15 10.2.10 three-phase waveform mode i/o pins ................................................................ 10-16 10.2.11 pin p6out cut (three-phase waveform-output-forcibly-cutoff signal input pin) .. 10-16 10.3 three-phase mode 0 ....................................................................................................... 10-17 10.3.1 setting for three-phase mode 0 ............................................................................. 10-17 10.3.2 operation in three-phase wave mode 0 ............................................................... 10-21 10.4 three-phase mode 1 ....................................................................................................... 10-26 10.4.1 setting for three-phase mode 1 ............................................................................. 10-26 10.4.2 operation in three-phase wave mode 1 ............................................................... 10-30 10.5 three-phase waveform output fixation ...................................................................... 10-33 10.6 position-data-retain function ........................................................................................ 10-35 10.6.1 operation of position-data-retain function ............................................................. 10-35 [precautions for three-phase waveform mode] ................................................................. 10-36 chapter 11. serial i/o 11.1 overview .............................................................................................................................. 1 1-2 11.2 block description .............................................................................................................. 11-3 11.2.1 uarti transmit/receive mode register .................................................................... 11-4 11.2.2 uarti transmit/receive control register 0 ............................................................... 11-6 11.2.3 uarti transmit/receive control register 1 ............................................................... 11-8 11.2.4 uarti transmit register and uarti transmit buffer register ............................. 11-10 11.2.5 uarti receive register and uarti receive buffer register ................................ 11-12 11.2.6 uarti baud rate register (brgi) ........................................................................... 11-14 11.2.7 uarti transmit interrupt control and uarti receive interrupt control registers . 11-15 11.2.8 serial i/o pin control register ................................................................................. 11-17 11.2.9 port p8 direction register ........................................................................................ 11-18 11.2.10 cts/rts function .................................................................................................. 11-19 11.3 clock synchronous serial i/o mode ........................................................................... 11-20 11.3.1 transfer clock (synchronizing clock) ..................................................................... 11-20 11.3.2 transfer data format ................................................................................................ 11-22 11.3.3 method of transmission ........................................................................................... 11-23
7906 group user? manual rev.2.0 v table of contents 11.3.4 transmit operation ................................................................................................... 11-26 11.3.5 method of reception ................................................................................................. 11-28 11.3.6 receive operation .................................................................................................... 11-31 11.3.7 processing on detecting overrun error .................................................................. 11-34 [precautions for clock synchronous serial i/o mode] .................................................... 11-35 11.4 clock asynchronous serial i/o (uart) mode ........................................................... 11-36 11.4.1 transfer rate (frequency of transfer clock) ......................................................... 11-37 11.4.2 transfer data format ................................................................................................ 11-39 11.4.3 method of transmission ........................................................................................... 11-40 11.4.4 transmit operation ................................................................................................... 11-44 11.4.5 method of reception ................................................................................................. 11-47 11.4.6 receive operation .................................................................................................... 11-50 11.4.7 processing on detecting error ................................................................................ 11-52 11.4.8 sleep mode ............................................................................................................... 11-53 [precautions for clock asynchronous serial i/o (uart) mode] .................................... 11-54 chapter 12. a-d converter 12.1 overview .............................................................................................................................. 1 2-2 12.2 block description .............................................................................................................. 12-4 12.2.1 a-d control registers 0, 1 ......................................................................................... 12-5 12.2.2 a-d register i (i = 0 to 4) ......................................................................................... 12-8 12.2.3 comparator function select register 0, comparator result register 0 .................. 12-9 12.2.4 a-d conversion interrupt control register .............................................................. 12-10 12.2.5 port p7 direction register ........................................................................................ 12-11 12.3 a-d conversion method ................................................................................................. 12-12 12.4 absolute accuracy and differential non-linearity error .......................................... 12-15 12.4.1 absolute accuracy .................................................................................................... 12-15 12.4.2 differential non-linearity error ................................................................................. 12-16 12.5 comparison voltage in 8-bit resolution mode .......................................................... 12-17 12.6 comparator function ....................................................................................................... 12-18 12.7 one-shot mode ................................................................................................................. 12-19 12.7.1 settings for one-shot mode .................................................................................... 12-19 12.7.2 one-shot mode operation ....................................................................................... 12-21 12.8 repeat mode ..................................................................................................................... 12-22 12.8.1 settings for repeat mode ........................................................................................ 12-22 12.8.2 repeat mode operation ........................................................................................... 12-24 12.9 single sweep mode ......................................................................................................... 12-25 12.9.1 settings for single sweep mode ............................................................................ 12-25 12.9.2 single sweep mode operation ................................................................................ 12-27 12.10 repeat sweep mode 0 .................................................................................................. 12-28 12.10.1 settings for repeat sweep mode 0 ...................................................................... 12-28 12.10.2 repeat sweep mode 0 operation ........................................................................ 12-30 [precautions for a-d converter] ............................................................................................ 12-31 chapter 13. d-a converter 13.1 overview .............................................................................................................................. 1 3-2 13.2 block description .............................................................................................................. 13-2 13.2.1 d-a control register ................................................................................................... 13-3 13.2.2 d-a register i (i = 0, 1) ........................................................................................... 13-3
7906 group user? manual rev.2.0 vi table of contents 13.3 d-a conversion method ................................................................................................... 13-4 13.4 setting method ............................................................................................................ ....... 13-5 13.5 operation description ....................................................................................................... 13-5 [precautions for d-a converter] .............................................................................................. 13-6 chapter 14. watchdog timer 14.1 block description .............................................................................................................. 14-2 14.1.1 watchdog timer .......................................................................................................... 14-3 14.1.2 watchdog timer frequency select register .............................................................. 14-3 14.1.3 particular function select register 2 ......................................................................... 14-4 14.2 operation description ....................................................................................................... 14-5 14.2.1 basic operation ........................................................................................................... 14-5 14.2.2 stop period ................................................................................................................. 14-7 14.2.3 operations in stop mode .......................................................................................... 14-7 [precautions for watchdog timer] ........................................................................................... 14-8 chapter 15. stop and wait modes 15.1 overview .............................................................................................................................. 1 5-2 15.2 block description .............................................................................................................. 15-3 15.2.1 particular function select register 0 ......................................................................... 15-4 15.2.2 particular function select register 1 ......................................................................... 15-6 15.2.3 watchdog timer frequency select register .............................................................. 15-7 15.3 stop mode ........................................................................................................................... 15-8 15.3.1 terminate operation at interrupt request occurrence (when using watchdog timer) ... 15-8 15.3.2 terminate operation at interrupt request occurrence (when not using watchdog timer) 15-9 15.3.3 terminate operation at hardware reset ................................................................. 15-11 15.4 wait mode ......................................................................................................................... 15-12 15.4.1 terminate operation at interrupt request occurrence .......................................... 15-12 15.4.2 terminate operation at hardware reset ................................................................. 15-12 chapter 16. power saving functions 16.1 overview .............................................................................................................................. 1 6-2 16.1.1 particular function select register 0 ......................................................................... 16-3 16.1.2 particular function select register 1 ......................................................................... 16-5 16.2 inactivity of system clock in wait mode ....................................................................... 16-6 16.3 stop of oscillation circuit ................................................................................................ 16-7 16.4 pin v ref disconnection ..................................................................................................... 16-7 chapter 17. debug function 17.1 overview .............................................................................................................................. 1 7-2 17.2 block description .............................................................................................................. 17-2 17.2.1 debug control register 0 ........................................................................................... 17-3 17.2.2 debug control register 1 ........................................................................................... 17-4 17.2.3 address compare registers 0 and 1 ........................................................................ 17-5 17.3 address matching detection mode ............................................................................... 17-6 17.3.1 setting procedure for address matching detection mode ..................................... 17-6 17.3.2 operations in address matching detection mode .................................................. 17-7
7906 group user? manual rev.2.0 vii table of contents 17.4 out-of-address-area detection mode ............................................................................... 17-10 17.4.1 setting procedure for out-of-address-area detection mode ............................... 17-10 17.4.2 operations in out-of-address-area detection mode ............................................. 17-11 [precautions for debug function] ......................................................................................... 17-12 chapter 18. applications 18.1 application examples ....................................................................................................... 18-2 18.1.1 application example of air-conditioner outdoor unit .............................................. 18-2 18.1.2 application example of refrigerator .......................................................................... 18-3 18.1.3 application example of washing machine ............................................................... 18-4 chapter 19. flash memory version 19.1 overview .............................................................................................................................. 1 9-2 19.1.1 memory assignment ................................................................................................... 19-4 19.1.2 single-chip mode ........................................................................................................ 19-6 19.1.3 boot mode ................................................................................................................... 19-8 19.2 flash memory cpu reprogramming mode .................................................................. 19-9 19.2.1 flash memory control register ............................................................................... 19-10 19.2.2 status register .......................................................................................................... 19-12 19.2.3 s etting and terminate procedure for flash memory cpu reprogramming mode ..... 19-13 19.2.4 software commands ................................................................................................ 19-14 19.2.5 full status check ...................................................................................................... 19-16 19.2.6 electrical characteristics .......................................................................................... 19-17 [precautions for flash memory cpu reprogramming mode] ......................................... 19-18 19.3 flash memory serial i/o mode ..................................................................................... 19-19 19.3.1 pin description .......................................................................................................... 19-19 19.3.2 example of handling control pins in flash memory serial i/o mode ................ 19-23 [precautions for flash memory serial i/o mode] .............................................................. 19-25 19.4 flash memory parallel i/o mode ................................................................................. 19-26 [precautions for flash memory parallel i/o mode] ........................................................... 19-27 appendix appendix 1. memory assignment in sfr area .................................................................... 20-2 appendix 2. control registers ............................................................................................... 20-10 appendix 3. package outline ................................................................................................. 20-44 appendix 4. examples of handling unused pins .............................................................. 20-45 appendix 5. hexadecimal instruction code table ............................................................. 20-46 appendix 6. machine instructions ........................................................................................ 20-54 appendix 7. countermeasure against noise ...................................................................... 20-96 appendix 8. 7906 group q & a .......................................................................................... 20-102 appendix 9. m37906m4c-xxxfp electrical characteristics .......................................... 20-109 appendix 10. m37906m4c-xxxfp standard characteristics ........................................ 20-117 appendix 11. memory assignment of 7906 group ......................................................... 20-122
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chapter 1 description 1.1 performance overview 1.2 pin configuration 1.3 pin description 1.4 block diagram
description 7906 group user? manual rev.2.0 1-2 items number of basic instructions instruction execution time external clock input frequency f(x in ) system clock frequency f(f sys ) memory sizes rom ram programmable p1, p2 input/output ports p5 p6 p7 multifunctional ta0?a9 timer tb0?b2 serial i/o uart0, uart1 a-d converter d-a converter watchdog timer interrupt maskable non-maskable clock generating circuit pll frequency multiplier power source voltage power dissipation port input/output input/output withstand voltage characteristics output current memory expansion operating ambient temperature range device structure package m37906m4c-xxxfp m37906m4c-xxxsp 1.1 performance overview 1.1 performance overview table 1.1.1 lists the performance overview of the m37906m4c-xxxfp/sp. table 1.1.1 m37906m4c-xxxfp/sp performance overview performance 203 50 ns (the minimum instruction at f(f sys ) = 20 mhz) 20 mhz (maximum) 20 mhz (maximum) 32 kbyte 1024 bytes 8 bits ? 2 3 bits ? 1 6 bits ? 1 5 bits ? 1 16 bits ? 10 16 bits ? 3 (uart or clock synchronous serial i/o) ? 2 10-bit successive approximation method ? 1 (5 channels) 8 bits ? 2 12 bits ? 1 5 external, 18 internal (any of priority levels 0 through 7 can be set for each interrupt, by software.) 3 internal built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) double, triple, or quadruple 5 v ?0.5 v 125 mw (at f(f sys ) = 20 mhz 5 v 5 ma not available. (single-chip mode only) ?0 ? to 85 ? cmos high-performance silicon gate process 42-pin plastic molded ssop (42p2r-e) 42-pin shrink plastic molded sdip (42p4b)
description 7906 group user? manual rev.2.0 1-3 1.2 pin configuration 1.2 pin configuration figures 1.2.1 and 1.2.2 show the m37906m4c-xxxfp/sp pin configuratios. fig. 1.2.1 m37906m4c-xxxfp pin configuration (outline 42p2r-e, top view) outline 42p2r-e avss 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 v ref p7 4 /an 4 /da 1 /int 3 /rtp trg0 p7 3 /an 3 /da 0 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 md0 v cont vcc avcc p1 2 /r x d 0 p1 3 /t x d 0 p1 6 /r x d 1 p1 7 /t x d 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 4 (/tb0 in ) p2 5 (/tb1 in ) p2 6 (/tb2 in ) md1 x out x in vss p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 reset p2 7 (/int 3 /rtp trg0 ) p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 1 /cts 0 /clk 0 p1 0 /cts 0 /rts 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw note p6out cut /int 4 note note note: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switched by software.
description 7906 group user? manual rev.2.0 1-4 1.2 pin configuration fig. 1.2.2 m37906m4c-xxxsp pin configuration (outline 42p4b, top view) outline 42p4b p1 0 /cts 0 /rts 0 avss 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 v ref p7 4 /an 4 /da 1 /int 3 /rtp trg0 p7 3 /an 3 /da 0 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 md0 v cont vcc avcc p1 2 /r x d 0 p1 3 /t x d 0 p1 6 /r x d 1 p1 7 /t x d 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 4 (/tb0 in ) p2 5 (/tb1 in ) p2 6 (/tb2 in ) md1 x out x in vss p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 reset p2 7 (/int 3 /rtp trg0 ) p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 1 /cts 0 /clk 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw note note note p6out cut /int 4 note: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switched by software.
description 7906 group user? manual rev.2.0 1-5 apply 5 v ?0.5 v to pin vcc and 0 v to pin vss. this pin switches the operating mode. this is only for the single-chip mode, so connect this pin to v ss . the microcomputer is reset when ??level is input to this pin. pins x in and x out are the input and output pins of the clock generating circuit, respectively. connect these pins via a ceramic resonator or a quartz-crystal oscillator. when an external clock is input, this clock should be input to pin x in , and pin x out should be left open. to use the pll frequency multiplier, be sure to connect this pin to the filter circuit. the power source input pin for the a-d converter. connect this pin to vcc. the power source input pin for the a-d and d-a converters. connect this pin to vss. this is the reference voltage input pin for the a-d and d-a converters. p0 is an 8-bit cmos i/o port and has an i/o direction register. each pin can function as an input or output port pin. by software, these pins can function as i/o pins for serial i/o. p2 is an 8-bit i/o port with the same function as port p1. by software, these pins can function as i/o pins for timers a4 and a9. also, these pins can function as input pins for timers b0 to b2, input pins for the external interrupts, or trigger input pins in the pulse output port mode. p5 is a 3-bit i/o port with the same function as port p1. by software, t hese pins can function as input pins for timers b0 to b2, input pins for external interrupts, or position data input pins in the three-phrase waveform mode. p6 is a 6-bit i/o port with the same function as port p1. by software, these pins can function as i/o pins for timers a0 to a2, or as motor drive waveform output pins. p7 is a 5-bit i/o port with the same function as port p1. by software, these pins can function as input pins for the a-d converter, output pins for the d-a converter, input pins for the external interrupts, or trigger input pins in the pulse output port mode. this pin has the function to forcibly place port p6 pins in the input mode (port-output-cutoff function). also, this pin functions as an input pin for int 4 , and as an input pin for the port-output- cutoff function in the motor drive waveform output mode. 1.3 pin description input input input output input i/o i/o i/o i/o i/o input input/output power source input md0 md1 reset input clock input clock output filter circuit connection analog power source input reference voltage input i/o port p1 i/o port p2 i/o port p5 i/o port p6 i/o port p7 p6out cut input vcc, vss md0 md1 reset x in x out v cont avcc avss v ref p1 0 ?1 7 p2 0 ?2 7 p5 5 ?5 7 p6 0 ?6 5 p7 0 ?7 4 p6out cut 1.3 pin description tables 1.3.1 lists the pin description. table 1.3.1 pin description name pin function
description 7906 group user? manual rev.2.0 1-6 1.4 block diagram 1.4 block diagram figure 1.4.1 shows the m37906 block diagram. fig. 1.4.1 m37906 block diagram md1 v ref av ss av cc v cc x in x out md0 v ss v cont p6out cut central processing unit (cpu) arithmetic logic unit (16) accumulator a (16) accumulator b (16) index register x (16) index register y (16) stack pointer s (16) direct page register dpr3 (16) direct page register dpr2 (16) direct page register dpr1 (16) direct page register dpr0 (16) processor status register ps (11) input buffer register ib (16) data bank register dt (8) program bank register pg (8) program counter pc (16) incrementer/decrementer (24) bus interface unit (biu) data address register da (24) program address register pa (24) incrementer (24) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) instruction queue buffer q 7 (8) instruction queue buffer q 6 (8) instruction queue buffer q 5 (8) instruction queue buffer q 4 (8) instruction queue buffer q 3 (8) instruction queue buffer q 2 (8) instruction queue buffer q 1 (8) instruction queue buffer q 0 (8) data buffer dq 3 (8) data buffer dq 2 (8) data buffer dq 1 (8) data buffer dq 0 (8) data bus (even) data bus (odd) address bus reference voltage input (0v) instruction register (8) (0v) reset reset input clock output clock generating circuit clock input input/output port p7 input/output port p6 input/output port p5 input/output port p2 input/output port p1 p1(8) p2(8) p5(3) p6(6) p7(5) timer tb0 (16) timer tb1 (16) timer tb2 (16) watchdog timer uart0 (9) uart1 (9) a-d converter (10) d-a 0 converter (8) d-a 1 converter (8) timer ta0 (16) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta5 (16) timer ta6 (16) timer ta7 (16) timer ta8 (16) timer ta9 (16) ram rom
chapter 2 central processing unit (cpu) 2.1 central processing unit (cpu) 2.2 bus interface unit (biu) 2.3 access space 2.4 memory assignment 2.5 processor modes [precautions for setting of processor mode]
7906 group user? manual rev.2.0 central processing unit (cpu) 2.1 central processing unit (cpu) 2-2 2.1 central processing unit (cpu) the cpu (central processing unit) has 13 registers shown in figure 2.1.1. fig. 2.1.1 cpu registers direct page register 1 (dpr1) d p r 1 h d p r 1 l b 1 5b 8b 7b0 a c c u m u l a t o r b ( b ) b h b l b 1 5 b 8b 7b 0 a c c u m u l a t o r e ( e ) e b 3 1 b0 i n d e x r e g i s t e r x ( x ) x h x l b 1 5 b 8b 7b0 i n d e x r e g i s t e r y ( y ) y h y l b 1 5 b 8b 7b0 stack pointer (s) s h s l b 1 5 b 8b 7b0 d a t a b a n k r e g i s t e r ( d t ) d t b 7b 0 d i r e c t p a g e r e g i s t e r 0 ( d p r 0 ) dpr0 h dpr0 l b 1 5b 8b 7b0 b15 b8 b7 b0 b23 b16 p r o g r a m c o u n t e r ( p c ) program bank register (pg) pc h pc l p g b7 b0 a c c u m u l a t o r a ( a ) a h a l b 1 5 b8 b7 b0 d i r e c t p a g e r e g i s t e r 2 ( d p r 2 ) d p r 2 h d p r 2 l b 1 5b 8b 7b0 direct page register 3 (dpr3) d p r 3 h d p r 3 l b15 b8 b7 b0 p r o c e s s o r s t a t u s r e g i s t e r ( p s ) ps h p s l b15 b8 b7 b0 b 0 b1 b2 b3 b 4 b5 b 6 b 7 b 8 b 1 0 b 1 5 c z i d x m v n ip l 0 0 0 0 0 c a r r y f l a g zero flag i n t e r r u p t d i s a b l e f l a g d e c i m a l m o d e f l a g index register length flag d a t a l e n g t h f l a g overflow flag n e g a t i v e f l a g p r o c e s s o r i n t e r r u p t p r i o r i t y l e v e l
7906 group user s manual rev.2.0 2.1 central processing unit (cpu) central processing unit (cpu) 2-3 2.1.1 accumulator (acc) accumulators a and b are available. also, accumulators a and b can be connected in series in order to be used as a 32-bit accumulator (accumulator e). (1) accumulator a (a) accumulator a is the main register of the microcomputer. the transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator a. it consists of 16 bits, and the low-order 8 bits can also be used separately. the data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. flag m is a part of the processor status register, which is described later. when an 8-bit register is selected, only the low-order 8 bits of accumulator a are used, and the contents of the high-order 8 bits is unchanged. (2) accumulator b (b) accumulator b is a 16-bit register with the same function as accumulator a. accumulator b can be used instead of accumulator a. the use of accumulator b, however except for some instructions, requires more instruction bytes and execution cycles than those of accumulator a. accumulator b is also affected by flag m just as in accumulator a. (3) accumulator e (e) this 32-bit accumulator consists of accumulator a located in the low-order 16 bits and accumulator b located in the high-order 16 bits. this accumulator is used by an instruction that handles 32-bit data. it is not affected by flag m. 2.1.2 index register x (x) index register x consists of 16 bits and the low-order 8 bits can also be used separately. the index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. flag x is a part of the processor status register, which is described later. when an 8-bit register is selected, only the low-order 8 bits of index register x are used, and the contents of the high-order 8 bits are not unchanged. in an addressing mode in which index register x is used as an index register, the address obtained by adding the contents of this register to the operand s contents is accessed. also, each of the mvp , mvn and rmpa instructions uses index register x. ? refer to ?900 series software manual for addressing modes and instructions. 2.1.3 index register y (y) index register y is a 16-bit register with the same function as index register x. just as in index register x, this register is affected by flag x.
7906 group user s manual rev.2.0 central processing unit (cpu) 2.1 central processing unit (cpu) 2-4 2.1.4 stack pointer (s) the stack pointer (s) is a 16-bit register. it is used for a subroutine call or an interrupt. it is also used when addressing modes using the stack are executed. the contents of s indicate an address (stack area) for storing registers during subroutine calls and interrupts. bank 016 is specified for the stack area. (refer to section ?.3 access space. ) when an interrupt request is accepted, the microcomputer stores the contents of the program bank register (pg) at the address indicated by the contents of s and decrements the contents of s by 1. then the contents of the program counter (pc) and the processor status register (ps) are stored. the contents of s after accepting an interrupt request is equal to the contents of s decremented by 5 before accepting of fig. 2.1.2 contents of stack area after accepting interrupt request s i s t h e i n i t i a l a d d r e s s t h a t t h e s t a c k p o i n t e r ( s ) i n d i c a t e s a t a c c e p t i n g a n i n t e r r u p t r e q u e s t . t h e s s c o n t e n t s b e c o m e s 5 a f t e r s t o r i n g t h e a b o v e r e g i s t e r s . a d d r e s s s 4 s 3 s 2 s 1 s s t a c k a r e a s 5 p r o c e s s o r s t a t u s r e g i s t e r s l o w - o r d e r b y t e ( p s l ) processor status register s high-order byte (ps h ) program counter s low-order byte (pc l ) program counter s high-order byte (pc h ) program bank register (pg) the interrupt request. (see figure 2.1.2.) when completing the process in the interrupt routine and returning to the original routine, the contents of registers stored in the stack area are restored into the original registers in the reverse sequence (ps pc pg) by executing the rti instruction. the contents of s is returned to the state before accepting an interrupt request. the same operation is performed during a subroutine call, however, the contents of ps is not automatically stored. (the contents of pg may not be stored. this depends on the addressing mode.) during interrupts or subroutine calls, the other registers are not automatically stored. therefore, if the contents of these registers need to be held on, be sure to store them by software. additionally, the s s contents become 0fff 16 at reset. the stack area changes when subroutines are nested or when multiple interrupt requests are accepted. therefore, make sure of the subroutine s nesting depth not to destroy the necessary data. ? refer to 7900 series software manual for addressing modes and instructions.
7906 group user s manual rev.2.0 2.1 central processing unit (cpu) central processing unit (cpu) 2-5 2.1.5 program counter (pc) the program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. the contents of the high-order program counter (pc h ) become ff 16 , and the low-order program counter (pc l ) becomes fe 16 at reset. the contents of the program counter becomes the contents of the reset s vector address (addresses fffe 16 , ffff 16 ) just after reset. figure 2.1.3 shows the program counter and the program bank register. fig. 2.1.3 program counter and program bank register 2.1.6 program bank register (pg) the memory space is divided into units of 64 kbytes. this unit is called bank. (refer to section ?.3 access space. ) the program bank register is an 8-bit register that indicates the high-order 8 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. these 8 bits indicate a bank. when a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. when a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. therefore, there is no need to consider bank boundaries during programming, usually. this register is cleared to 00 16 at reset. p c h p c l b 7b 0 b15 b 8b 7b 0 (b16) p g ( b 2 3 ) 2.1.7 data bank register (dt) the data bank register is an 8-bit register. in the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. use the ldt instruction when setting a value to this register. this register is cleared to 00 16 at reset. addressing modes using data bank register direct indirect direct indexed x indirect direct indirect indexed y absolute absolute indexed x absolute indexed y absolute bit relative stack pointer relative indirect indexed y multiplied accumulation ? refer to ?900 series software manual for addressing modes.
7906 group user s manual rev.2.0 central processing unit (cpu) 2.1 central processing unit (cpu) 2-6 2.1.8 direct page register 0 to 3 (dpr0 to dpr3) each of direct page registers 0 to 3 (hereafter called the dpri ) is a 16-bit register. the contents of this register specify the direct page area in bank 0 16 or in the space across banks 0 16 and 1 16 . the following addressing modes use dpri. the contents of the dpri indicate the base address (the lowest address) of the direct page area. the direct page area is specified in the space above this address. after reset, whether to use dpr0 only or dpr0 to dpr3 can be selected by the direct page register switch bit. (see figure 2.1.5). this selection specifies the direct page area. table 2.1.1 lists the selection of the direct page register. figure 2.1.4 shows setting examples of the direct page area. at reset, dpr0 = 0000 16 , and each of dpr1 to dpr3 becomes undefined. addressing modes using direct page register table 2.1.1 selection of direct page register usable dpri direct page area direct page register switch bit 0 dpr0 256 bytes 1 dpr0 to dpr3 64 bytes at each dpri fig. 2.1.4 setting examples of direct page area direct direct indexed x direct indexed y direct indirect direct indexed x indirect direct indirect indexed y direct indirect long direct indirect long indexed y direct bit relative ? refer to ?900 series software manual for addressing modes and instructions. 1000f 16 10000 16 1000f 16 bank 0 16 0 16 0 16 ff 16 123 16 222 16 ff10 16 10000 16 ffff 16 when dpr0 = 0000 16 when dpr0 = 0123 16 when dpr0 = ff10 16 note: when the low-order 8 bits of dpri = 00, the number of cycles required for address generation becomes 1 cycle smaller. the direct page area is specified in space across banks 0 16 and 1 16 when dpr0 is ff01 16 or more. direct page register switch bit = 0 0 16 3f 16 40 16 7f 16 ffd0 16 ffff 16 bank 0 16 when dpr0 = 0000 16 when dpr1 = 0040 16 when dpr3 = ffd0 16 800 16 83f 16 when dpr2 = 0800 16 direct page register switch bit = 1 0 16 the direct page area is specified in the space across banks 0 16 and 1 16 when dpri is ffc1 16 or more. bank 1 16 bank 1 16
7906 group user s manual rev.2.0 2.1 central processing unit (cpu) central processing unit (cpu) 2-7 fig. 2.1.5 structure of processor mode register 1 0 1 6 to 2 7 rw rw rw rw 1 0 0 0 processor mode register 1 (address 5f 16 ) bit name bit function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 : only dpr0 is used. 1 : dpr0 through dpr3 are used. 0 : 3 1 : 2 this bit may be either 0 or 1. direct page register switch bit fix these bits to 00000. internal rom bus cycle select bit (note 2) x : it may be either 0 or 1. notes 1: after reset, this bit is allowed to be changed only once. (during the software execution, be sure not to change this bit s content.) 2: to reprogram the internal flash memory by using the cpu reprogramming mode, clear this bit to 0. (refer to section 19.2 flash memory cpu reprogramming mode. ) x 0 0000
7906 group user s manual rev.2.0 central processing unit (cpu) 2.1 central processing unit (cpu) 2-8 2.1.9 processor status register (ps) ps is an 11-bit register. figure 2.1.6 shows the structure of ps. refer to 7900 series software manual for detale about the change of each bit. fig. 2.1.6 structure of ps (1) bit 0: carry flag (c) this flag retains a carry or a borrow generated in the arithmetic and logic unit (alu) during an arithmetic operation. this flag is also affected by shift and rotate instructions. be sure to use the sec or sep instruction to set this flag to 1 ; and be sure to use the clc or clp instruction to clear it to 0 . the contents of this flag is undefined at reset. (2) bit 1: zero flag (z) this flag is set to 1 when the result of an arithmetic operation or data transfer is 0, and cleared to 0 when otherwise. this flag is invalid in the decimal arithmetic operation. be sure to use the sep instruction to set this flag to 1 ; and be sure to use the clp instruction to clear it to 0. the contents of this flag is undefined at reset. (3) bit 2: interrupt disable flag (i) this flag disables all maskable interrupts except the following: the address matching detection, watchdog timer, and 0 division interrupts. interrupts are disabled when this flag is 1. when an interrupt request has been accepted, this flag is automatically set to 1, and multiple interrupts become disabled. be sure to use the sei or sep instruction to set this flag to 1 ; and be sure to use the cli or clp instruction to clear this flag to 0. this flag is set to 1 at reset. (4) bit 3: decimal mode flag (d) this flag determines whether addition and subtraction are performed in binary or decimal. binary arithmetic operation is performed when this flag is 0. when it is 1, decimal arithmetic operation is performed with each 8 bits treated as 2-digit decimal (at m = 1) or each 16 bits treated as 4-digit decimal (at m = 0). decimal adjust is automatically performed. decimal operation is possible only with the adc, adcb, sbc and sbcb instructions. be sure to use the sep instruction to set this flag to 1 ; and be sure to use the clp instruction to clear it to 0. this flag is cleared to 0 at reset. (5) bit 4: index register length flag (x) this flag determines whether each of index register x and index register y is used as a 16-bit register or an 8-bit register. that register is used as a 16-bit register when this flag is 0, and as an 8-bit register when it is 1 (note) . be sure to use the sep instruction to set this flag to 1 ; and be sure to use the clp instruction to clear it to 0. this flag is cleared to 0 at reset. b15 b8 b7 b0 b1 b2 b3 b4 b5 b6 b14 b9 b10 b11 b12 b13 0nc z i d x m v 0ipl 0 0 0 note: be sure to fix bits 15 through 11 to 0. processor status register (ps)
7906 group user s manual rev.2.0 2.1 central processing unit (cpu) central processing unit (cpu) 2-9 (6) bit 5: data length flag (m) this flag determines whether to use data as a 16-bit unit or as an 8-bit unit. each data is treated as a 16-bit unit when this flag is 0, and as an 8-bit unit when it is 1 (note) . be sure to use the sem or sep instruction to set this flag to 1, and be sure to use the clm or clp instruction to clear it to 0. this flag is cleared to 0 at reset. note: when transferring data between registers which are different in bit length, this data is transferred with the length of the transfer destination register, except for the case where the txa , tya , txb , tyb , and txs instructions used. refer to 7900 series software manual for detail. (7) bit 6: overflow flag (v) this flag is used when addition or subtraction is performed with a word regarded as signed binary. the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 2147483648 and +2147483647 (when 32-bit length operation), the range between 32768 and +32767 (when 16-bit length operation), or the range between 128 and +127 (when 8-bit length operation). the overflow flag is also set to 1 when the operation result of the div or divs instruction exceeds the length of the register which will store that result. this flag is invalid in the decimal mode. be sure to use the sep instruction to set this flag to 1, and be sure to use the clv or clp instruction to clear it to 0. the contents of this flag is undefined at reset. (8) bit 7: negative flag (n) this flag is set to 1 when the result of arithmetic operation or data transfer is negative. (the most significant bit of the result is 1. ) it is cleared to 0 in all other cases. this flag is invalid in the decimal mode. be sure to use the sep instruction to set this flag to 1, and be sure to use the clp instruction to clear it to 0. the contents of this flag is undefined at reset. (9) bits 10 to 8: processor interrupt priority level (ipl) these 3 bits can determine the processor interrupt priority level to one of levels 0 through 7. when the interrupt priority level of a requested interrupt, which has been set in the corresponding interrupt control register, is higher than ipl, that interrupt becomes enabled. when an interrupt request is accepted, ipl is stored in the stack area, and ipl is replaced by the interrupt priority level of the accepted interrupt request. there are no instruction to directly set or clear the bits of ipl. ipl can be changed by storing the new ipl into the stack area and updating ps with the pul or plp instruction. the contents of ipl is cleared to 000 2 at reset.
central processing unit (cpu) 7906 group user? manual rev.2.0 2-10 2.2 bus interface unit (biu) fig. 2.2.1 bus and biu 2.2 bus interface unit (biu) the bus interface unit (hereafter called ?iu? performs the following two operations: instruction prefetch data transfer (read and write) figure 2.2.1 shows the bus and biu. biu is structured with four kinds of registers shown in figure 2.2.2. table 2.2.1 lists the function of the biu registers. m37906 internal code bus (cb 0 to cb 31 ) (cpu) sfr : special function register ? the cpu bus and internal bus are independent of one another. internal control signal internal buses internal data bus (db 0 to db 15 ) internal address bus (ad 0 to ad 23 ) (biu) cpu bus central processing unit bus interface unit internal memory internal peripheral devices (sfr) program address register instruction queue buffer data address register data buffer pa da q 0 q 9 dq b23 b0 b0 b0 b0 b23 b31 b7 name program address register instruction queue buffer data address register data buffer functions indicates a storage address of the instruction to be fetched into an instruction queue buffer, next. temporarily stores an instruction which has been fetched. indicates an address from which data will be read or to which data will be written, next. temporarily stores data which has been read from memory i/o device by biu or which will be written to memory i/o device by the cpu. fig. 2.2.2 biu registers?structure table 2.2.1 functions of biu registers in the m37906, the internal buses are used when the cpu accesses the internal area (the internal memory and sfr).
central processing unit (cpu) 7906 group user s manual rev.2.0 2-11 2.2 bus interface unit (biu) 2.2.1 instruction prefetch while the cpu does not use the internal buses, the biu reads instructions from the memory and then stores them in the instruction queue buffer. the cpu reads instructions from the instruction queue buffer and executes them, so that the cpu can operate at high speed without access to the memory, which requires a long access time. the instruction queue buffer can store instructions up to 10 bytes. the contents of the instruction queue buffer is initialized when a branch is made, and the biu reads a new instruction from the branch destination address. when instructions in the instruction queue buffer are insufficient for the cpu s needs, the biu extends the low-level duration of cpu (see figure 4.2.1.) in order to keep the cpu waiting until the biu fetches instructions of the required byte number or more. figure 2.2.3 shows operating waveform examples at instruction prefetch. note that the operation of biu s instruction prefetch also varies with the store addresses of instructions. table 2.2.2 lists the store address of prefetched instructions. when the instruction prefetch from internal memory, the instructions are fetched from 4-byte boundaries, 4 bytes at a time. (see figure 2.2.3.) also, at branch, regardless of the low-order 2 bits contents (ad 1 and ad 0 ) of the branch destination address, 4 bytes are fetched at time from the 4- byte boundaries. (see figure 2.2.3.) in this case, 4-byte boundaries 8-byte boundaries even-numbered address table 2.2.2 store address of prefetched instruction x: it may be either 0 or 1. ad 2 ? ? 0 ad 1 ? 0 0 ad 0 0 0 0 low-order 3 bits at store address out of the data (instructions) which will be output onto the internal code buses, 4 bytes at a time, the instructions assigned at the branch destination address and the following addresses will be fetched into the instruction queue buffer. accordingly, as listed in table 2.2.3, the number of bytes to be fetched into the instruction queue buffer varies according to the branch destination address. 4 3 2 1 table 2.2.3 number of bytes to be fetched into instruction queue buffer ad 0 0 1 0 1 ad 1 0 0 1 1 ad 1 0 0 0 0 low-order 2 bits of branch destination address low-order 2 bits of address to be output onto address bus number of bytes to be fetched into instruction queue buffer ad 0 0 0 0 0 internal address bus biu internal code bus (instruction) address biu : operation clock of biu (refer to chapter 4. clock generating circuit. ) data (ad 0 ad 23 ) (cb 0 cb 31 ) fig. 2.2.3 operation waveform examples at instruction prefetch note: this waveform applies when bus cycle = 2 . for details of the bus cycle at access to the internal area, see table 2.2.4.
central processing unit (cpu) 7906 group user s manual rev.2.0 2-12 2.2 bus interface unit (biu) 2.2.2 data transfer (read and write) when the cpu reads or writes data from or to the internal area, it requests the biu to read or write data. the biu outputs control signals in order to control the internal address and data buses in response to the request from the cpu. the cycle where the following are performed is referred to bus cycle : the biu controls buses. data transfer is performed between the internal area and biu. table 2.2.4 lists the bus cycles at access to the internal area. figure 2.2.4 shows operating waveform examples at reading from or writing to the internal area. (1) reading data the cpu informs the biu s data address register of the address where the data to be read is stored, so the cpu requests the data. in this case, the cpu waits until the requested data is ready in the biu. the biu outputs the address informed by the cpu onto the internal address bus. then, the cpu reads the contents of the informed address and takes them into the data buffer. the cpu continues processing using data in the data buffer. (2) writing data the cpu informs the biu s data address register of the address to which the data will be written, so the cpu writes the data into the data buffer. the biu outputs the address informed by the cpu onto the internal address bus. then, the biu writes the data in the data buffer into the informed address. table 2.2.4 bus cycles at access to internal area bus cycle = 3 (internal rom bus cycle select bit = 0) rom ram sf r internal address bus internal data bu s biu address 1 bus cycle = 2 biu internal address bus internal data bus address 1 bus cycle = 2 bus cycle = 2 (internal rom bus cycle select bit = 1) biu internal address bus internal data bu s data address 1 bus cycle = 3 data data internal rom bus cycle select bit: bit 7 at address 5f 16 note: we usually recommend to select bus cycle = 2 . when reprogramming the internal flash memory in the cpu reprogramming mode, be sure to select bus cycle = 3 . (refer to section 19.2 flash memory cpu reprogramming mode. )
central processing unit (cpu) 7906 group user s manual rev.2.0 2-13 2.2 bus interface unit (biu) internal address bus biu internal data bus internal data bus rd: data to be read, wd: data to be written note 2: the above waveforms apply when bus cycle = 2 . for the bus cycles at access to the internal area, see table 2.2.4. internal address bus (ad 0 ad 23 ) biu internal data bus (db 0 db 7 ) rd (even) (a) when accessing 8-bit data (note 1) or accessing 16-bit data starting from an even-numbered address internal data bus (db 8 db 15 ) rd (odd) wd (even) wd (odd) address wd (odd) internal address bus biu internal data bus internal data bus rd (odd) address address + 1 rd (even) wd (even) rd (odd) rd (even) wd (even) rd (even) wd (even) wd(odd) rd (odd) wd (odd) rd (odd) address address + 1 rd (even) wd (even) address + 3 wd (odd) rd (odd) wd (even) wd (odd) note 1: when reading 8-bit data at an even-numbered address, only rd (even) will be taken into a data buffer. when reading 8-bit data at an odd-numbered address, only rd (odd) will be taken into a data buffer. when writing 8-bit data to an even-numbered address, only wd (even) will be written to the address. when writing 8-bit data to an odd-numbered address, only wd (odd) will be written to the address. internal address bus biu internal data bus internal data bus address address + 2 (b) when accessing 16-bit data starting from an odd-numbered address (c) when accessing 32-bit data starting from an even-numbered address (d) when accessing 32-bit data starting from an odd-numbered address rd (even) (ad 0 ad 23 ) (db 0 db 7 ) (db 8 db 15 ) (ad 0 ad 23 ) (db 0 db 7 ) (db 8 db 15 ) (ad 0 ad 23 ) (db 0 db 7 ) (db 8 db 15 ) fig. 2.2.4 operation waveform examples at reading from or writing to internal area
7906 group user? manual rev.2.0 2-14 central processing unit (cpu) 2.3 access space the access space of the m37906 is assigned to a 16-mbyte space from addresses 0 16 to ffffff 16 . (see figure 2.3.1.) note that only the internal memory can be accessed because the m37906 operates only in the single-chip mode. the memory and i/o devices are assigned in the same access space. accordingly, it is possible to perform transfer and arithmetic operations using the same instructions, without discrimination of the memory from i/o devices. fig. 2.3.1 m37906? access space : nothing is assigned. 0 16 sfr area internal ram area (note 1) bank 0 16 internal rom area (note 2) ff 16 sfr : special function register notes 1: when the internal ram area is followed by an unused area, do not assign a program to the last 8 bytes of the internal ram area. 2: do not assign a program to the last 8 bytes of the internal rom area. 3: the memory assignment of the internal area varies according to the product type. refer to section appendix 11. memory assignment of 7906 group, or the latest datasheets, catalogs. 4: refer to section 19.1.1 memory assignment, about the flash memory version. : memory assignment of internal area 2.3 access space
7906 group user s manual rev.2.0 2-15 central processing unit (cpu) 2.4 memory assignment this section describes the memory assignment in the internal area. 2.4.1 memory assignment in internal area sfr (special function register), internal ram, and internal rom are assigned to the internal area. figure 2.4.1 shows the memory assignment in the internal area. (1) sfr area the registers used to set the internal peripheral devices are assigned to addresses 0 16 to ff 16 . this area is called sfr. figures 2.4.2 and 2.4.3 show the sfr area s memory assignment. for each register in the sfr area, refer to each functional description in this manual. for the state of the sfr area immediately after reset, refer to section 3.3 state of internal area. (2) internal ram area the internal ram area is used as a stack area, as well as an area to store data. accordingly, be sure to set the nesting depth of a subroutine and multiple interrupts level not to destroy the necessary data. when the internal ram area is followed by an unused area, do not assign a program to the last 8 bytes of the internal ram area. (data is allowed to be assigned there. also, when the internal ram area is followed by the internal rom area succeedingly, a program is allowed to be assigned there.) (3) internal rom area addresses ffb4 16 to ffff 16 are the vector addresses for reset and interrupts. (this is called the interrupt vector table.) do not assign a program to the last 8 bytes of the internal rom area. (data is allowed to be assigned there.) 2.4 memory assignment
7906 group user s manual rev.2.0 2-16 central processing unit (cpu) 2.4 memory assignment reserved area timer a7 timer a8 reserved area timer a9 timer a6 reserved area timer b2 watchdog timer reserved area reserved area reserved area reserved area timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 notes 1: these are interrupts only for debugging; do not use these interrupts. 2: memory assignment of the internal area varies according to the product type. refer to section appendix 11. memory assignment of 7906 group or the latest datasheets, catalogues. : the internal memory is not assigned. reset zero divide l h fffa 16 fffc 16 fffe 16 interrupt vector table ff 16 0 16 ffff 16 ffb4 16 internal ram area see figures 2.4.2 and 2.4.3. internal rom area sfr area l h l h brk instruction (note 1) fff8 16 l h dbc (note 1) fff6 16 l h fff4 16 l h fff2 16 l h fff0 16 l h ffee 16 l h ffec 16 l h ffea 16 l h ffe8 16 l h ffe6 16 l h ffe4 16 l h ffe2 16 l h ffe0 16 l h ffde 16 l h ffdc 16 l h uart0 receive ffda 16 l h uart0 transmit ffd8 16 l h uart1 receive ffd6 16 l h uart1 transmit ffd4 16 l h a-d conversion ffd2 16 l h int 3 ffd0 16 l h int 4 ffce 16 l h reserved area ffcc 16 l h reserved area ffca 16 l h address matching detection ffc8 16 l ffc6 16 l h ffc4 16 l h ffc2 16 l h ffc0 16 l h timer a5 h ffb6 16 ffbe 16 ffb4 16 ffb8 16 ffbc 16 ffba 16 int 7 int 6 int 5 l h l h l h l h l h l h fig. 2.4.1 memory assignment in internal area
7906 group user s manual rev.2.0 2-17 central processing unit (cpu) (note 2) port p5 register (note 2) port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) address uart1 transmit/receive mode register address uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 transmit buffer register uart1 transmit/receive control register 0 uart1 baud rate register (brg1) uart1 transmit/receive control register 1 uart0 receive buffer register uart1 transmit buffer register uart1 receive buffer register 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 a 16 b 16 c 16 d 16 e 16 f 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 28 16 29 16 2a 16 2b 16 2c 16 2d 16 2e 16 2f 16 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 3f 16 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 4a 16 4b 16 4c 16 4d 16 4e 16 4f 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 6a 16 6b 16 6c 16 6d 16 6e 16 6f 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 (note 2) port p1 register (note 2) port p1 direction register port p2 register (note 2) port p2 direction register (note 2) a-d control register 0 a-d control register 1 a-d conversion interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register (note 2) (note 2) (note 2) timer a clock division select register processor mode register 0 processor mode register 1 watchdog timer register watchdog timer frequency select register int 3 interrupt control register int 4 interrupt control register one-shot start flag 0 up-down flag 0 count start flag 0 timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register address (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) external interrupt input read register d-a control register d-a register 0 d-a register 1 80 16 81 16 82 16 83 16 84 16 85 16 86 16 87 16 88 16 89 16 8a 16 8b 16 8c 16 8d 16 8e 16 8f 16 90 16 91 16 92 16 93 16 94 16 95 16 96 16 97 16 98 16 99 16 9a 16 9b 16 9c 16 9d 16 9e 16 9f 16 particular function select register 0 particular function select register 1 particular function select register 2 (note 2) debug control register 0 debug control register 1 notes 1: do not read from and write to this register. 2: do not write to this register. 3: when these registers are accessed, set the address compare register access enable bit (bit 2 at address 67 16 ) to 1. (refer to chapter 17. debug function. ) 4: this register is assigned only to the flash memory version. (refer to chapter 19. flash memory version. ) nothing is assigned here in the mask rom version. address compare register 0 (note 3) address compare register 1 (note 3) (note 1) (note 1) flash memory control register (note 4) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) count start flag 1 one-shot start flag 1 2.4 memory assignment fig. 2.4.2 sfr area s memory map (1)
7906 group user s manual rev.2.0 2-18 central processing unit (cpu) fig. 2.4.3 sfr area s memory map (2) 2.4 memory assignment note 5: do not write to this register. address up-down flag 1 timer a5 register timer a6 register timer a7 register timer a8 register timer a9 register timer a0 1 register timer a1 1 register timer a2 1 register timer a5 mode register timer a6 mode register timer a7 mode register timer a8 mode register timer a9 mode register (note 5) comparator function select register 0 (note 5) comparator result register 0 (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) timer a5 interrupt control register timer a6 interrupt control register timer a7 interrupt control register timer a8 interrupt control register timer a9 interrupt control register int 5 interrupt control register int 6 interrupt control register int 7 interrupt control register address a0 16 a1 16 a2 16 a3 16 a4 16 a5 16 a6 16 a7 16 a8 16 a9 16 aa 16 ab 16 ac 16 ad 16 ae 16 af 16 b0 16 b1 16 b2 16 b3 16 b4 16 b5 16 b6 16 b7 16 b8 16 b9 16 ba 16 bb 16 bc 16 bd 16 be 16 bf 16 (note 5) (note 5) (note 5) (note 5) (note 5) clock control register 0 (note 5) (note 5) (note 5) serial i/o pin control register (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) port p2 pin function control register position-data-retain function control register three-phase output data register 0 three-phase output data register 1 dead-time timer waveform output mode register c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 ca 16 cb 16 cc 16 cd 16 ce 16 cf 16 d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 ea 16 eb 16 ec 16 ed 16 ee 16 ef 16 f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16
7906 group user? manual rev.2.0 2-19 central processing unit (cpu) 2.5 processor modes 2.5 processor modes the m37906 operates only in the single-chip mode. figure 2.5.1 shows the memory assignment of the m37906. unused area internal rom area (note 2) unused area 0 16 ff 16 sfr area single-chip mode internal ram area (note 1) notes 1: when the internal ram area is followed by an unused area, do not assign a program to the last 8 bytes of the internal ram area. 2: do not assign a program to the last 8 bytes of the internal rom area. 3: the memory assignment of the internal area varies according to the product type. refer to section ?ppendix 11. memory assignment of 7906 group, or the latest datasheets, catalogs. fig. 2.5.1 memory assignment of m37906 2.5.1 single-chip mode in this mode, ports p1, p2, p5 to p7 serve as programmable i/o ports. (when an internal peripheral device is used, the corresponding port pin serves as the device s i/o pin). in this mode, only the internal area (sfr, internal ram, and internal rom) can be accessed.
7906 group user s manual rev.2.0 2-20 central processing unit (cpu) 2.5 processor modes fig. 2.5.3 structure of processor mode register 0 2.5.2 setting of processor mode the processor mode is set by the following: voltage level applied to the md0 and md1 pins processor mode bits (bits 1 and 0 at address 5e 16 ) the v ss level voltage must be applied to the md0 and md1 pins, because the m37906 operates only in the single-chip mode. also, the processor mode bit must be 00. figure 2.5.2 shows the structure of the processor mode register 0 (address 5e 16 ). 0 1 2 3 4 5 6 7 bit name bit processor mode register 0 (address 5e 16 ) function at reset r/w processor mode bits interrupt priority detection time select bits software reset bit fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 0 : single-chip mode 0 1 : do not select. 1 0 : do not select. 1 1 : do not select. b1 b0 0 0 : 7 cycles of f sys 0 1 : 4 cycles of f sys 1 0 : 2 cycles of f sys 1 1 : do not select. b5 b4 the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 0 1 0 0 0 0 rw rw rw rw rw rw wo rw 0xx 0 0 any of these bits may be either 0 or 1. x : it may be either 0 or 1.
7906 group user s manual rev.2.0 2-21 central processing unit (cpu) [precautions for setting of processor mode] [precautions for setting of processor mode] the m37906 operates only in the single-chip mode. therefore, for the m37906, do as follows: the md0 and md1 pins must be connected to vss. the processor mode bits (bits 0 and 1 at address 5e 16 ) must be fixed to 00 2 .
7906 group user s manual rev.2.0 2-22 central processing unit (cpu) [precautions for setting of processor mode] memorandum
chapter 3 reset 3.1 reset operation 3.2 pin state 3.3 state of internal area 3.4 internal processing sequence after reset
reset 7906 group user? manual rev.2.0 3-2 there are 3 ways to reset the microcomputer: hardware reset : apply ??level of voltage to pin reset while the power source voltage (vcc) meets the recommended operating conditions. software reset : write ??to the software reset bit (bit 6 at address 5e 16 ) while the power source voltage (vcc) meets the recommended operating conditions. power-on reset : after power-on, raise the voltage level at pin vcc to the level, which meets the recommend operating conditions, with ??level of voltage applied to pin reset. 3.1 reset operation operations of hardware, software, and power-on reset are described below. 3.1.1 hardware reset figure 3.1.1 shows an example of hardware reset timing. fig. 3.1.1 example of hardware reset timing the following explains how the microcomputer operates in the above periods, ? to ? . ? after applying ??level of voltage to pin reset, the microcomputer initializes pins within a period of several ten cycles of f sys . (refer to section ?.2 pin state. ) ? the microcomputer initializes the central processing unit (cpu) and sfr area in the following periods. (refer to section ?.3 state of internal area. ) ?while pin reset is at ??level. ?in the period of 8 to 9 cycles of f sys after pin reset goes from ??to ?. ? after ? , the microcomputer performs internal processing sequence after reset. (refer to section ?.4 internal processing sequence after reset. ) ? the microcomputer executes a program beginning with the address which has been set into the reset vector addresses (addresses fffe 16 and ffff 16 ). reset 10 s or more 8 to 9 cycles of f sys internal processing sequence after reset program is executed. (note) ? ? ? ? note: the above is applied when the oscillator is stably oscillating or when an external clock is stably input from pin x in. when the oscillator is not stably oscillating (including the case at the stop mode s termination; refer to section 15.3 stop mode. ), apply l level of voltage for 10 s or more after the oscillation becomes stable. 3.1 reset operation
reset 7906 group user s manual rev.2.0 3-3 bit name bit processor mode register 0 (address 5e 16 ) function at reset r/w processor mode bits interrupt priority detection time select bits software reset bit fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 0 : single-chip mode 0 1 : do not select. 1 0 : do not select. 1 1 : do not select. b1 b0 0 0 : 7 cycles of f sys 0 1 : 4 cycles of f sys 1 0 : 2 cycles of f sys 1 1 : do not select. b5 b4 the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 1 2 3 4 5 6 7 0 0 0 1 0 0 0 0 rw rw rw rw rw rw wo rw fig. 3.1.2 structure of processor mode register 0 3.1.2 software reset the microcomputer initializes pins, cpu, and sfr area just as in the case of hardware reset (refer to sections 3.2 pin state and 3.3 state of internal area ) by writing 1 to the software reset bit. (see figure 3.1.2.) after initialization is completed, the microcomputer performs internal processing sequence after reset. (refer to section 3.4 internal processing sequence after reset. ) after that, it executes a program beginning with the address which has been set into the reset vector addresses (addresses fffe 16 and ffff 16 ). 3.1 reset operation 00 0 x x x: it may be either 0 or 1 . any of these bits may be either 0 or 1.
reset 7906 group user s manual rev.2.0 3-4 3.1.3 power-on reset the following describes the operation of the microcomputer at power-on reset. ? after powered on, within the several ten cycles of f sys after the voltage level at pin vcc meets the recommended operating conditions with the voltage level at pin reset = l, the microcomputer initializes pins; refer to section 3.2 pin state. ? after the voltage level at pin reset goes from l to h, the microcomputer initializes the cpu and sfr area within a period of 8 to 9 cycles of f sys . (contents of the internal ram area become undefined; refer to section 3.3 state of internal area. ) ? after ? , the microcomputer performs internal processing sequence after reset. ; refer to section 3.4 internal processing sequence after reset. ? the microcomputer executes a program beginning with the address which has been set into the reset vector addresses (addresses fffe 16 and ffff 16 ). fig. 3.1.4 example of power-on reset circuit 3.1 reset operation 1 v cc in out gnd delay capacity reset v cc v ss 47 ? sw c d gnd 3 25 5 v m51957al m37906 27 k ? 10 k ? 4 ? the delay time is about 11 ms when c d = 0.033 f. t d 0.34 ? c d [ s], c d : [pf] figure 3.1.3 shows the power-on reset conditions. figure 3.1.4 shows an example of a power-on reset circuit. after the voltage level at pin vcc meets the recommended operating conditions and the oscillator s operation is stabilized (see figure 3.1.3.), apply l level of voltage to pin reset for 10 s or more. when an oscillator is used, the time required for stabilizing oscillation depends on the oscillator. for details, contact the oscillator manufacturer. v cc reset powered on there v cc level 0.2 v cc level oscillation stabilized 10 s x in 0 v 0 v 0 v fig. 3.1.3 power-on reset conditions
reset 7906 group user s manual rev.2.0 3-5 vss vss vcc p1, p2, p5 p7 p1, p2, p5 p7 p1, p2, p5 p7 floating. floating. floating (note 2) . 3.2 pin state 3.2 pin state table 3.2.1 lists the microcomputer s pin state while the voltage level at pin reset is l. table 3.2.1 pin state while voltage level at pin reset is l notes 1: refer to chapter 19. flash memory version. 2: pins p5 6 , p5 7 and p6 0 to p6 5 output h or l level when h level of voltage is applied to pin v cont and l level to pins p7 0 , p7 1 . vss vcc mask rom version, flash memory version (note 1) flash memory version (note 1) pin state pin (bus, port) name pin md1 s level pin md0 s level
reset 7906 group user s manual rev.2.0 3-6 3.3 state of internal area figure 3.3.1 shows the state of cpu registers immediately after reset. figures 3.3.2 to 3.3.9 show the state of the sfr and internal ram areas immediately after reset. 3.3 state of internal area fig. 3.3.1 state of cpu registers immediately after reset 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. data bank register (dt) 00 16 b7 b0 program bank register (pg) 00 16 b7 b0 program counter (pc) contents at address fffe 16 contents at address ffff 16 b7 b0 b15 b8 direct page register 0 (dpr0) 00 16 b7 b0 00 16 b15 b8 processor status register (ps) 0 0 00 0 0 1 b7 b0 b15 b8 nv mxd izc ipl ? ?? ? stack pointer (s) ff 16 b7 b0 0f 16 b15 b8 index register y (y) ? b7 b0 ? b15 b8 index register x (x) ? b7 b0 ? b15 b8 accumulator b (b) ? b7 b0 ? b15 b8 accumulator a (a) ? b7 b0 ? b15 b8 register name state immediately after reset : 0 immediately after reset. fix this bit to 0. direct page register i (dpri) ? b7 b0 ? b15 b8 (i = 1 to 3) 0 0 0 0 0 0
reset 7906 group user s manual rev.2.0 3-7 3.3 state of internal area fig. 3.3.2 state of sfr and internal ram areas immediately after reset (1) 0 ? ? 00 0 0 000 0 0 00 0 000 0 0 ? 0 ?? : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. sfr area (addresses 0 16 to ff 16 ) rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1c 16 1b 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p5 register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register a-d control register 0 a-d control register 1 register name port p1 register port p1 direction register port p2 direction register port p2 register ? ? access characteristics state immediately after reset rw (note 2) rw rw rw (note 2) rw rw (note 2) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b7 b0 b7 b0 ? rw rw (note 2) (note 2) 00 16 ? ? 00 16 ? (note 2) rw (note 2) rw rw (note 2) rw (note 2) (note 2) (note 2) (note 2) ?? 00? 0 0 0 (note 1) (note 1) notes 1: do not read and write. 2: do not write. 0 0 ? ?
reset 7906 group user s manual rev.2.0 3-8 ? 0000 0 0 uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart1 receive buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (barg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 b7 b0 register name address access characteristics state immediately after reset b7 b0 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 rw rw ? 0000 0 0 ? 0000 0 0 ? 0000 0 0 rw wo wo ro ro wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro ro ro rw rw ? ? ? ? ? ? ? ? ? ? 0 1000 ? ? ? 00 16 ? ? ? ? 0000000 ? ? ? 00 16 0 0000010 0000 0 0 0 ? 1000 000000 1 0 (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 4) (note 4) (note 4) (note 4) (note 4) (note 4) 00 0 0000 ? 0000 0 0 notes 3: the access characteristics at addresses 20 16 to 29 16 vary according to the contents of the comparator function select register 0 (address dc 16 ). (refer to chapter 12. a-d converter. ) 4: do not write. fig. 3.3.3 state of sfr and internal ram areas immediately after reset (2) 3.3 state of internal area
reset 7906 group user s manual rev.2.0 3-9 0 0 0 0 00 1 00 ? 0 00 0 0 ? 0 0 0 timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start register 0 one-shot start register 1 timer a0 register up-down register 0 timer a1 register count start register 0 count start register 1 timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register wo wo b7 b0 rw rw rw rw rw rw rw rw rw rw wo ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 16 00 16 00 16 ? 00 16 b7 b0 ? ? 0 wo rw rw rw timer a0 mode register timer a4 mode register processor mode register 1 rw rw rw (note 7) 0 0 00 0 0 0 ? ? 00 ? 0 0 0 0 000 0 0 00 0 0 0 0 0 rw 0 0 00 0 0 00 (note 7) (note 7) 0 (note 5) (note 5) rw rw (note 5) (note 5) (note 6) (note 6) (note 6) (note 6) (note 5) (note 5) (note 5) (note 5) (note 6) (note 6) 1 0 0 0 0 0 0 0 0 0 00 16 00 16 rw rw timer a clock division select register 0 rw rw register name address access characteristics state immediately after reset notes 5: the access characteristics at addresses 46 16 to 4b 16 , 4e 16 , and 4f 16 vary according to the timer a s operating mode. (refer to chapter 7. timer a. ) 6: the access characteristics at addresses 50 16 to 55 16 vary according to the timer b s operating mode. (refer to chapter 8. timer b. ) 7: the access characteristics for bit 5 at addresses 5b 16 to 5d 16 vary according to the timer b s operating mode. (refer to chapter 8. timer b. ) 0 0 0 000 0 fig. 3.3.4 state of sfr and internal ram areas immediately after reset (3) 3.3 state of internal area
reset 7906 group user s manual rev.2.0 3-10 fig. 3.3.5 state of sfr and internal ram areas immediately after reset (4) 3.3 state of internal area 0 0 ? ? ? ? 0 rw 1 0 (note 12) uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 a-d conversion interrupt control register uart0 transmit interrupt control register uart1 transmit interrupt control register watchdog timer frequency select register watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register b7 b0 b7 uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register debug control register 0 int 4 interrupt control register rw (note 8) rw rw rw rw rw rw rw rw rw (note 13) (note 13) (note 13) rw rw rw rw rw b0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (note 9) 0 0 0 0000 0 0 0 0 0000 ? 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000 0 rw rw rw rw int 3 interrupt control register debug control register 1 rw rw ro ? ? (note 12) 00 00 0 ? particular function select register 0 particular function select register 1 00 0 (note 12) (note 11) ro ro rw rw rw rw rw rw (note 14) rw (note 14) rw (note 14) rw (note 14) rw (note 14) rw (note 14) address comparison register 0 address comparison register 1 0 rw (note 10) 0 (note 13) particular function select register 2 register name address access characteristics state immediately after reset notes 8 : by writing dummy data to address 60 16 , a value of fff 16 is set to the watchdog timer. the dummy data is not retained anywhere. 9 : a value of fff 16 is set to the watchdog timer. (refer to chapter 14. watchdog timer. ) 10 : after writing 55 16 to address 62 16 , each bit must be set. 11 : it is possible to read the bit state at reading. by writing 0 to this bit, this bit becomes 0. but when writing 1 to this bit, this bit will not change. 12 : this bit becomes 0 at power-on reset. this bit retains the state immediately before reset in the case of hardware reset and software reset. 13 : do not write. 14 : when these registers are accessed, set the address comparison register access enable bit (bit 2 at address 67 16 ) to 1. (refer to chapter 17. debug function. ) 0 0 00 00 0 ? 0 0 0
reset 7906 group user s manual rev.2.0 3-11 fig. 3.3.6 state of sfr and internal ram areas immediately after reset (5) ro 0 80 16 81 16 82 16 83 16 84 16 85 16 86 16 87 16 88 16 89 16 90 16 91 16 92 16 93 16 94 16 95 16 96 16 97 16 98 16 99 16 9a 16 9b 16 9c 16 9d 16 9e 16 9f 16 8b 16 8c 16 8d 16 8e 16 8f 16 8a 16 b7 b0 b7 b0 rw rw ro (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (note 15) (note 15) flash memory control register (note 16) d-a register 1 d-a register 0 d-a control register external interrupt input read-out register 0 0 0 0 1 rw rw rw rw rw register name address access characteristics state immediately after reset notes 15 : do not write. 16 : this register is allocated only to the flash memory version. (refer to chapter 19. flash memory version. ) this is not allocated to the mask rom version. 0 0 00 16 00 16 3.3 state of internal area
reset 7906 group user s manual rev.2.0 3-12 fig. 3.3.7 state of sfr and internal ram areas immediately after reset (6) ? ? 00 000 0 00 0 0 ? a0 16 a1 16 a2 16 a3 16 a4 16 a5 16 a6 16 a7 16 a8 16 a9 16 b0 16 b1 16 b2 16 b3 16 b4 16 b5 16 b6 16 b7 16 b8 16 b9 16 ba 16 bb 16 bc 16 bd 16 be 16 bf 16 ab 16 ac 16 ad 16 ae 16 af 16 aa 16 b7 b0 b7 b0 wave output mode register dead-time timer three-phase output data register 0 three-phase output data register 1 position-data-retain function control register serial i/o pin control register port p2 pin function control register clock control register 0 rw rw rw rw 00 16 00 16 00 16 0 00 00 00 00 ? ? ? ? ? ? ? rw rw rw rw rw ro ro ro rw rw wo rw rw ? ? ? ? ? 10 01 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes 17 : do not write to this register. 18 : after reset, these bits are allowed to be changed only once. (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) register name address access characteristics state immediately after reset rw rw rw rw (note 18) rw rw 3.3 state of internal area
reset 7906 group user s manual rev.2.0 3-13 rw rw 0 0 b7 b0 b7 b0 wo 0 00 comparator function select register 0 comparator result register 0 0 00 00 0 0 0 (note 19) (note 19) (note 20) (note 20) (note 20) rw rw rw rw rw wo wo wo wo wo wo rw 0 0 0 0 00 00 0 0 0 rw rw rw rw rw rw rw rw address register name access characteristics state immediately after reset up-down register 1 timer a5 register timer a6 register timer a7 register timer a8 register timer a9 register timer a0 1 register timer a1 1 register timer a2 1 register timer a5 mode register timer a6 mode register timer a7 mode register timer a8 mode register timer a9 mode register notes 19 : the access characteristics at addresses ce 16 and cf 16 vary according to the timer a s operating mode. (refer to chapter 7. timer a. ) 20 : do not write. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 16 00 16 00 16 00 16 00 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 ca 16 cb 16 cc 16 cd 16 ce 16 d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 cf 16 3.3 state of internal area fig. 3.3.8 state of sfr and internal ram areas immediately after reset (7)
reset 7906 group user s manual rev.2.0 3-14 3.3 state of internal area e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 b7 b0 b7 b0 int 5 interrupt control register int 6 interrupt control register int 7 interrupt control register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rw 00 00 00 0 rw 0 0 00 0 rw 0 00 0 rw 0 00 0 rw 0 00 0 rw 0 rw 00 00 0 rw 00 00 0 0 0 0 address register name access characteristics state immediately after reset timer a5 interrupt control register timer a6 interrupt control register timer a7 interrupt control register timer a8 interrupt control register timer a9 interrupt control register notes 21 : do not write to this register. (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) internal ram area at hardware reset ................................................................................. retains the state immedia tely before reset (note 22) . at software reset.................................................................................................... retains the state immediately before reset. at termination of the stop or wait mode (when hardware reset is used for the termination.)....................................retains the state immediately before t he stp or wit instruction is executed. at power-on reset............................................................................................................ ......................................... undefined. notes 22 : when a reset operation starts while writing to the internal ram area is in process, the microcomputer will be reset before the completion of writing. accordingly, the contents of the area where the writing was in process will become undefined. fig. 3.3.9 state of sfr and internal ram areas immediately after reset (8)
reset 7906 group user s manual rev.2.0 3-15 0000 16 00 16 fffe 16 ad 15 to ad 0 ipl, vector addresses of reset 00 16 00 16 undefined next op-code f sys : system clock (see figure 4.2.1.) ad 0 to ad 15 : internal address bus ipl : processor interrupt priority level ? this is an internal signal and is not output to the external. f sys a h(cpu) a l a m(cpu) data (cpu) ? ? ? ? ad 15 to ad 0 3.4 internal processing sequence after reset fig. 3.4.1 internal processing sequence after reset 3.4 internal processing sequence after reset figure 3.4.1 shows the internal processing sequence after reset.
reset 7906 group user s manual rev.2.0 3-16 3.4 internal processing sequence after reset memorandum
chapter 4 clock generating circuit 4.1 oscillation circuit examples 4.2 clocks [precautions for clcok generating circuit]
clock generating circuit 7906 group user? manual rev.2.0 4-2 4.1 oscillation circuit examples 4.1 oscillation circuit examples to the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. oscillation circuit examples are shown below. 4.1.1 connection example with resonator/oscillator figure 4.1.1 shows an example where pins x in and x out connect across a ceramic resonator/quartz-crystal oscillator. the circuit constants such as r f , r d , c in , and c out (shown in ?igure 4.1.1 ) depend on the resonator/ oscillator. these values shall be set to the values recommended by the resonator/oscillator manufacturer. fig. 4.1.1 connection example of resonator/oscillator fig. 4.1.2 externally generated clock input example m37906 x in x out r f c in c out r d m37906 x in x out vcc vss externally generated clock open 4.1.2 externally generated clock input example figure 4.1.2 shows an input example of a clock which is externally generated. an external clock must be input from pin x in , and pin x out must be left open. when an externally generated clock is input, the power source current consumption can be saved by the stop of internal circuit s operation between pins x in and x out . (refer to ?hapter 16. power saving function. )
clock generating circuit 7906 group user s manual rev.2.0 4-3 4.1 oscillation circuit examples 4.1.3 connection example of filter circuit in the usage of the pll frequency multiplier, be sure to connect a filter circuit with pin v cont . figure 4.1.3 shows a connection example of the filter circuit. fig. 4.1.3 connection example of filter circuit m37906 v cont 1 k ? 0.1 f 220pf note: connect the elements of the filter circuit as close as possible and enclose the whole circuit with a vss pattern.
clock generating circuit 7906 group user s manual rev.2.0 4-4 4.2 clocks 4.2 clocks figure 4.2.1 shows the clock generating circuit block diagram. fig. 4.2.1 clock generating circuit block diagram f 2 f 64 f 512 f 4096 q r s stp instruction biu (clock for biu) cpu (clock for cpu) cpu wait request 1/4 1/8 1/8 reset watchdog timer frequency select bit : bit 0 at address 61 16 watchdog timer clock source select bits at stp termination : bits 6, 7 at address 61 16 external clock input select bit : bit 1 at address 62 16 system clock stop select bit at wit : bit 3 at address 63 16 pll circuit operation enable bit : bit 1 at address bc 16 pll multiplication ratio select bits : bits 2, 3 at address bc 16 system clock select bit : bit 5 at address bc 16 peripheral device s clock select bits 0, 1 : bits 6, 7 at address bc 16 1/8 1/2 1/16 watchdog timer wf 32 wf 512 f 16 f 1 peripheral device s clocks 0 1 watchdog timer frequency select bit x in x out system clock stop select bit at wit 1/16 0 1 watchdog timer clock source select bits at stp termination 1 wait mode 1 0 1 0 1/2 1 0 1 wait mode system clock select bit pll frequency multiplier f pll v cont wait mode external clock input select bit q r s stp instruction interrupt request q r s wit instruction interrupt request wait mode pll circuit operation enable bit pll multiplication ratio select bits fx in f/n 0 fx 16 fx 32 fx 64 fx 128 fx 16 fx 32 fx 64 fx 128 peripheral device s clock select bit 0 peripheral device s clock select bit 1 biu : bus interface unit cpu : central processing unit ? : signal generated when the watchdog timer s most significant bit becomes 0. f sys system clock frequency select bit ? operating clock for serial i/o, timer b a-d conversion frequency ( ad ) clock source operating clock for timer a external clock input select bit interrupt request
clock generating circuit 7906 group user s manual rev.2.0 4-5 4.2.1 clocks generated in clock generating circuit (1) fx in it is the input clock from pin x in . (2) f pll it is the output clock from the pll frequency multiplier. (3) f sys it is the system clock which becomes the clock source of cpu, biu, and internal peripheral devices. whether fx in = f sys or f pll = f sys can be selected by software. (4) cpu it is the operating clock of cpu. (5) biu it is the operating clock of biu. (6) clock 1 it has the same period as f sys . (7) f 1 , f 2 , f 16 , f 64 , f 512 , f 4096 each of them is the internal peripheral device s operating clock. (8) wf 32 , wf 512 these are the operating clocks of the watchdog timer, and their clock source is f 2 . (9) fx 16 , fx 32 , fx 64 , fx 128 each of them is the divide clock of fx in and becomes the watchdog timer s clock source at stp termination. 4.2 clocks
clock generating circuit 7906 group user s manual rev.2.0 4-6 4.2 clocks 4.2.2 clock control register 0 figure 4.2.2 shows the structure of the clock control register 0, and figure 4.2.3 shows the setting procedure for the clock control register 0 when using the pll frequency multiplier. 1 1 1 0 1 0 0 0 clock control register 0 (address bc 16 ) bit name bit function at reset r/w fix this bit to 1. pll circuit operation enable bit (note 1) pll multiplication ratio select bits (note 2) fix this bit to 1. system clock select bit (note 3) peripheral device s clock select bit 0 peripheral device s clock select bit 1 b7 b6 b5 b4 b3 b2 b1 b0 0 : pll frequency multiplier is inactive, and pin v cont is invalid. (floating) 1 : pll frequency multiplier is active, and pin v cont is valid. 0 0 : do not select. 0 1 : ? 2 1 0 : ? 3 1 1 : ? 4 b3 b2 see table 4.2.2. 0 : fx in 1 : f pll 1 1 notes 1: clear this bit to 0 if the pll frequency multiplier needs not to be active. in the stop and flash memory parallel i/o modes, the pll frequency multiplier is inactive and pin v cont is invalid regard- less of the contents of this bit. 2: rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to 0 . then, set bit 5 to 1 2 ms after the rewriting of these bits. (after reset, these bits are allowed to be changed only once.) 3: clearance of the pll circuit operation enable bit (bit 1) to 0 clears the system clock select bit to 0. also, while the pll circuit operation enable bit = 0, nothing can be written to the system clock select bit. (fixed to be 0. ) before setting of set the system clock select bit to 1 after reset, it is necessary to insert an interval of 2 ms after the stabilization of f(x in ). 0 1 2 3 4 5 6 7 fig. 4.2.2 structure of clock control register rw rw rw rw rw rw rw rw (1) pll circuit operation enable bit (bit 1) setting this bit to 1 enables the pll frequency multiplier to be active and pin v cont to be valid. this bit = 1 while pin reset = l level and after reset, so that, in this case, the pll frequency multiplier is active. clear this bit to 0 if the pll frequency multiplier need not to be active. note that, in the stop and flash memory parallel i/o modes, the pll frequency multiplier is in active and pin v cont is invalid regardless of the contents of this bit. (refer to sections 15.3 stop mode and 19.4 flash memory parallel i/o mode. ) (2) pll multiplication ratio select bits (bits 2, 3) these bits select the multiplication ratio of the pll frequency multiplier. (see table 4.2.1.) to rewrite these bits, clear the system clock select bit (bit 5) to 0 simultaneously. then, set the system clock select bit to 1 2 ms after the rewriting of this bit. (see figure 4.2.3.) note that, after reset, these bits are allowed to be changed only once.
clock generating circuit 7906 group user s manual rev.2.0 4-7 1 4.2 clocks (3) system clock select bit (bit 5) this bit selects a clock source of f sys . when this bit = 0, fx in is selected as f sys ; and when this bit = 1, f pll as the one. (see table 4.2.1.) clearing the pll circuit operation enable bit (bit 1) to 0 clears the system clock select bit to 0. also, while the pll circuit operation enable bit = 0, nothing can be written to the system clock select bit. (fixed to be 0. ) in order to set the system clock select bit to 1 after reset, it is necessary to wait 2 ms after the stabilization of f(x in ). to rewrite the pll multiplication ratio select bits (bits 2 and 3), clear the system clock select bit to 0 simultaneously. then, set this bit to 1 2 ms after the rewriting of the pll multiplication ratio select bits. (see figure 4.2.3.) system clock select bit (bit 5) pll multiplication ratio select bits (bits 3, 2) (note 1) f sys 0 1 01 (double) 10 (triple) 11 (quadruple) f(x in ) f(x in ) ? 2 f(x in ) ? 3 f(x in ) ? 4 pll circuit operation enable bit (bit 1) clock source frequency (note 2) fx in f pll f pll f pll f sys /2 f sys /4 f sys /32 f sys /128 f sys /1024 f sys /8192 do not select. internal peripheral device s operation clock 00 peripheral device s clock select bits 1, 0 f 1 f 2 f 16 f 64 f 512 f 4096 f sys f sys /2 f sys /16 f sys /64 f sys /512 f sys /4096 01 10 11 f sys f sys f sys /8 f sys /32 f sys /256 f sys /2048 (note) table 4.2.1 f sys selection notes 1: the pll multiplication ratio select bits must be set so that f sys is in the range from 10 mhz to 20 mhz. after reset, these bits are allowed to be changed only once. 2: be sure that f sys does not exceed 20 mhz. table 4.2.2 internal peripheral device s operation clock frequency (4) peripheral device s clock select bits 1, 0 (bits 7, 6) these bits select the internal peripheral device s operation clock frequency listed in table 4.2.2. note: to set the peripheral device s clock select bits 1, 0 to 01 2 , be sure that a frequency of f sys must be 10 mhz or less.
clock generating circuit 7906 group user s manual rev.2.0 4-8 4.2 clocks fig. 4.2.3 setting procedure for clock control register 0 when using pll frequency multiplier 2 ms elapsed ? b0 clock control register 0 (address bc 16 ) b7 11 1 system clock select bit 0 : f pll setting of system clock select bit to 1. n y (note 2) notes 1: after reset, these bits are allowed to be changed only once. if it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 2: this decision is unnecessary if double is selected and the period of reset = l is the oscillation stabilizing time of an oscillator + 2 ms or more. b0 clock control register 0 (address bc 16 ) b7 pll multiplication ratio select bits (note 1) 0 1 : double 1 0 : triple 1 1 : quadruple 00 1 b3 b2 system clock select bit 0 : fx in pll frequency multiplier is active, and pin v cont is valid. 1 1
clock generating circuit 7906 group user s manual rev.2.0 4-9 4.2 clocks rw (note) rw (note) rw 0 0 0 bit name bit 0 1 7 to 2 particular function select register 0 (address 62 16 ) function at reset r/w stp instruction invalidity select bit external clcok input select bit fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 : stp instruction is valid. 1 : stp instruction is invalid. 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = 0, watchdog timer is not used at stop mode termination. when the system clock select bit = 1, watchdog timer is used at stop mode termination. 00 0 00 0 4.2.3 particular function select register 0 figure 4.2.4 shows the structure of the particular function select register 0, and figure 4.2.5 shows the writing procedure for the particular function select register 0. fig. 4.2.4 structure of particular function select register 0 note: writing to these bits requires the following procedure: write 55 16 to this register. (the bit status does not change only by this writing.) succeedingly, write 0 or 1 to each bit. also, use the movmb ( movm when m = 1) instruction or stab ( sta when m = 1) instruction. if an interrupt occurs between writing of 55 16 and next writing of 0 or 1, latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bit s contents after writing of 0 or 1, and verify whether 0 or 1 has correctly been written or not.
clock generating circuit 7906 group user s manual rev.2.0 4-10 (1) external clock input select bit (bit 1) when this bit is 0, the oscillation driver circuit between pins x in and x out operates. at the stop mode termination owing to an interrupt request occurrence, the watching timer is used. setting this bit to 1 stops the oscillation driver circuit between pins x in and x out and keeps the output level at pin x out being h. (refer to section 16.3 stop of oscillation circuit. ) at the stop mode termination owing to an interrupt request occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address bc 16 ) = 0, where as the watchdog timer is used if the system clock select bit = 1. to rewrite this bit, write 0 or 1 just after writing of 55 16 to address 62 16 . (see figure 4.2.5.) note that if an interrupt occurs between writing of 55 16 and next writing of 0 or 1, latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bit s contents after writing of 0 or 1, and verify whether 0 or 1 has correctly been written or not. in addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16 ), the watchdog timer can be active only at the stop mode termination if this bit = 0. (refer to section 15.3 stop mode. ) 4.2 clocks fig. 4.2.5 writing procedure for particular function select register 0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa 00 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa 0 writing of 55 16 b0 particular function select register 0 (address 62 16 ) b7 1 setting completed aaa aaa aaa 1 0 writing to bits 0, 1 b0 particular function select register 0 (address 62 16 ) b7 external clock input select bit 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = 0, watchdog timer is not used at stop mode termination. when the system clock select bit = 1, watchdog timer is used at stop mode termination. stp instruction invalidity select bit 0 : stp instruction is valid. 1 : stp instruction is invalid. next instruction note: bits state does not change only by writing of 55 16 . 00 0 00 0 1 1 0 0
clock generating circuit 7906 group user s manual rev.2.0 4-11 [precautions for clock generating circuit] [precautions for clock generating circuit] 1. while pin reset = l level and after reset, the pll frequency multiplier is inactive. clear the pll circuit operation enable bit (bit 1 at address bc 16 ) to 0 if the pll frequency multiplier needs not to be active. 2. to select f pll as f sys after reset, set the system clock select bit (bit 5 at address bc 16 ) to 1 2 ms after f(x in ) has been stabilized. (see figure 4.2.3.) 3. to change the multiplication ratio for the pll frequency multiplier, clear the system clock select bit (bit 5 at address bc 16 ) to 0 simultaneously. then, set the system clock select bit to 1 2 ms after the rewriting of the pll multiplication ratio select bits (bits 2, 3 at address bc 16 ). (see figure 4.2.3.) after reset, the pll multiplication ratio select bits are allowed to be changed only once. if it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset.
clock generating circuit 7906 group user s manual rev.2.0 4-12 [precautions for clock generating circuit] memorandum
chapter 5 input/output pins 5.1 overview 5.2 programmable i/o ports 5.3 examples of handling unused pins
input/output pins 7906 group user? manual rev.2.0 5-2 5.1 overview, 5.2 programmable i/o ports 5.1 overview input/output pins (hereafter called i/o pins) have functions as programmable i/o port pins, internal peripheral devices? i/o pins, etc. for the basic functions of each i/o pin, refer to section ?.3 pin description. for the i/o functions of the internal peripheral devices, refer to relevant sections of each internal peripheral device. this chapter describes the programmable i/o ports and examples of handling unused pins. 5.2 programmable i/o ports the programmable i/o ports have direction registers and port registers in the sfr area. figure 5.2.1 shows the memory map of direction registers and port registers. fig. 5.2.1 memory map of direction registers and port registers addresses port p2 register port p5 register port p7 register port p6 register port p1 register port p2 direction register port p1 direction register port p6 direction register port p5 direction register port p7 direction register 3 16 4 16 5 16 6 16 7 16 8 16 9 16 a 16 b 16 c 16 d 16 e 16 f 16 10 16 11 16 (note) (note) (note) (note) (note) note: do not write to this address.
input/output pins 7906 group user s manual rev.2.0 5-3 5.2 programmable i/o ports 5.2.1 direction register this register determines the i/o direction of programmable i/o ports. one bit of this register corresponds to one pin of the microcomputer, and this is the one-to-one relationship. figure 5.2.2 shows the structure of port pi (i = 1, 2, 5 to 7) direction register. fig. 5.2.2 structure of port pi (i = 1, 2, 5 to 7) direction register 0 1 2 3 4 5 6 7 port pi direction register (i = 1, 2, 5 to 7) (addresses 5 16 , 8 16 , d 16 , 10 16 , 11 16 ) port pi 0 direction bit port pi 1 direction bit port pi 2 direction bit port pi 3 direction bit port pi 4 direction bit port pi 5 direction bit port pi 6 direction bit port pi 7 direction bit 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 notes 1: nothing is assigned for bits 0 to 4 of the port p5 direction register. these bits are undefined at reading. 2: nothing is assigned for bits 6 and 7 of the port p6 direction register. these bits are undefined at reading. 3: nothing is assigned for bits 5 to 7 of the port p7 direction register. these bits are undefined at reading. 4: any of bits 0 to 5 of the port p6 direction register becomes 0 by input of a falling edge to pin p6out cut /int 4 . (refer to section 5.2.3 pin p6out cut /int 4 . ) 0 : input mode (the port functions as an input port.) 1 : output mode (the port functions as an output port.) bit name bit function at reset r/w
input/output pins 7906 group user s manual rev.2.0 5-4 5.2 programmable i/o ports 5.2.2 port register data is input from or output to the external by writing/reading data to/from a port register. a port register consists of a port latch which holds the output data and a circuit which reads the pin state. one bit of the port register corresponds to one pin of the microcomputer. (this is the one-to-one relationship.) figure 5.2.3 shows the structure of the port pi (i = 1, 2, 5 to 7) register. when outputting data from programmable i/o port which has been set to output mode ? by writing data to the corresponding bit of the port register, the data is written into the port latch. ? the data is output from the pin according to the contents of the port latch. by reading the port register of a port which has been set to the output mode, the contents of the port latch is read out, instead of the pin state. accordingly, the output data can be correctly read out without being affected by an external load, etc. (see figures 5.2.4 and 5.2.5. ) when inputting data from programmable i/o port which has been set to input mode ? a pin which has been set to the input mode enters the floating state. ? by reading the corresponding bit of the port register, the data which has been input from the pin can be read out. by writing data to a port register of a programmable i/o port which has been set to the input mode, the data is written only into the port latch and is not output to the external (note) . this pin remains floating state. note: when executing a read-modify-write instruction to a port register of a programmable i/o port which has been set to the input mode, the instruction will be executed to the data which has been input from the pin and the result will be written into the port register. fig. 5.2.3 structure of port pi (i = 1, 2, 5 to 7) register rw rw rw rw rw rw rw rw bit name bit 0 1 2 3 4 5 6 7 port pi register (i = 1, 2, 5 to 7) (addresses 3 16 , 6 16 , b 16 , e 16 , f 16 ) funtion at reset r/w port pin pi 0 port pin pi 1 port pin pi 2 port pin pi 3 port pin pi 4 port pin pi 5 port pin pi 6 port pin pi 7 undefined undefined undefined undefined undefined undefined undefined undefined b7 b6 b5 b4 b3 b2 b1 b0 notes 1: nothing is assigned for bits 0 to 4 of the port p5 register. these bits are undefined at reading. 2: nothing is assigned for bits 6 and 7 of the port p6 register. these bits are undefined at reading. 3: nothing is assigned for bits 5 to 7 of the port p7 register. these bits are undefined at reading. data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : l level 1 : h level
input/output pins 7906 group user s manual rev.2.0 5-5 5.2 programmable i/o ports figures 5.2.4 and 5.2.5 show the port peripheral circuits. fig. 5.2.4 port peripheral circuits (1) [inside dotted-line included] [inside dotted-line not included] p1 3 /t x d 0 , p1 7 /t x d 1 p2 0 /ta4 out , p2 2 /ta9 out data bus data bus data bus data bus port latch direction register output (internal peripheral device) output (internal peripheral device) 1 p7 0 /an 0 , p7 1 /an 1 p7 2 /an 2 analog input p1 2 /r x d 0 , p1 6 /r x d 1 p2 1 /ta4 in , p2 3 /ta9 in p2 4 (/ tb 0 in ), p 2 5 (/ tb 1 in ) p2 6 (/ tb 2 in ), p 2 7 (/ i nt 3 /r tp trg 0 ) p5 5 /int 5 /tb0 in /idw p5 6 /int 6 /tb1 in /idv p5 7 /int 7 /tb2 in /idu p6 0 /ta0 out /w/r tp0 0 p6 1 /ta0 in /v/r tp0 1 p6 2 /ta1 out /u/r tp0 2 p6 3 /ta1 in /w/r tp0 3 p6 4 /ta2 out /v/r tp1 0 p6 5 /ta2 in /u/r tp1 1 1 r p6out cut reset direction register direction register direction register port latch port latch port latch
input/output pins 7906 group user? manual rev.2.0 5-6 enable d-a output p7 3 /an 3 /da 0 p7 4 /an 4 /da 1 /int 3 /rtp trg 0 p1 0 /cts 0 /r ts 0 p1 1 /cts 0 /clk 0 p1 4 /cts 1 /r ts 1 p1 5 /cts 1 /clk 1 1 0 p6out cut /int 4 port latch port latch direction register direction register data bus data bus output (internal peripheral device) analog input analog output [inside dotted-line included] [inside dotted-line not included] fig. 5.2.5 port peripheral circuits (2) 5.2 programmable i/o ports 5.2.3 pin p6out cut /int 4 (port-p6-output-cutoff signal input pin) any of bits 0 through 5 of the port p6 direction register (address 10 16 ) are forcibly cleared to 0 by input of a falling edge to pin p6out cut /int 4 , regardless of the mode of port pins p6 0 through p6 5 ; therefore, port pins p6 0 through p6 5 enter the input mode. after that, if it is necessary to output data from port pins p6 0 through p6 5 , be sure to do as follows: ? return the input level at pin p6out cut /int 4 to h level. ? write data to the port p6 register (address e 16 ) s bits, corresponding to the port p6 pins which will output data. ? set the port p6 direction register s bits, corresponding to the port p6 pins in ? , to 1 in order to set these port pins to the output mode. when input level at pin p6out cut /int 4 is l , no bit of the port p6 direction register can be set to 1. when using port pins p6 0 through p6 5 as output port pins at all the time, connect pin p6out cut /int 4 to vcc via a resistor. pin p6out cut /int 4 cannot serve as pin int 4 . also, when using pin p6out cut /int 4 as an input pin of an external interrupt (pin int 4 ), use port pins p6 0 through p6 5 in the input mode.
input/output pins 7906 group user s manual rev.2.0 5-7 5.3 examples of handling unused pins 5.3 examples of handling unused pins when unusing an i/o pin, some handling is necessary for this pin. examples of handling unused pins are described below. the following are just examples. in actual use, the user shall modify them according to the user s application and properly evaluate their performance. table 5.3.1 example of handling unused pins notes 1: when leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. therefore, voltage levels of these pins are undefined and the power source current may increase while these port pins are placed in the input mode. software reliability can be enhanced by setting the contents of the above ports direction registers periodically. this is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputer s pins). 2: this applies when a clock externally generated is input to pin x in . 3: be sure that the pll circuit operation enable bit (bit 1 at address bc 16 ) = 0. fig. 5.3.1 example of handling unused pins p1, p2, p5 to p7 m37906 left open left open left open v cc v cc v ss p1, p2, p5 to p7 m37906 av cc av ss v ref x out v cont av cc av ss v ref x out v cont v ss v cc v cc p6out cut /int 4 p6out cut /int 4 when setting port pins to input mode when setting port pins to output mode handling example set these pins to the input mode and connect each pin to vcc or vss via a resistor; or set these pins to the output mode and leave them open (note 1). connect this pin to vcc via a resistor. select a falling edge for pin int 4 . leave these pins open. connect this pin to vcc. connect these pins to vss. pin name p1, p2, p5 to p7 p6out cut /int 4 x out (note 2) , v cont (note 3) av cc av ss , v ref
input/output pins 7906 group user s manual rev.2.0 5-8 5.3 examples of handling unused pins memorandum
chapter 6 interrupts 6.1 overview 6.2 interrupt sources 6.3 interrupt control 6.4 interrupt priority level 6.5 interrupt priority level detection circuit 6.6 interrupt priority level detection time 6.7 sequence from acceptance of interrupt request until execution of interrupt routine 6.8 return from interrupt routine 6.9 multiple interrupts 6.10 external interrupts [precautions for interrupts]
7906 group user? manual rev.2.0 interrupts 6-2 when an interrupt request is accepted, the following registers?contents just before acceptance of an interrupt request are automatically pushed onto the stack area in ascending sequence from ? to ? . for other registers of which contents are necessary, be sure to push and pop them by software. ? program bank register (pg) ? program counter (pc l , pc h ) ? processor status register (ps l , ps h ) figure 6.1.2 shows the state of the stack area just before entering an interrupt routine. execute the rti instruction at the end of this interrupt routine in order to return to the routine that the microcomputer was executing just before the interrupt request was accepted. by executing the rti instruction, the register contents pushed onto the stack area are pulled in descending sequence from ? to ? . then, the suspended processing is resumed from where it left off. 6.1 overview the m37906 provides 27 (including the reset) interrupt sources to generate interrupt requests. figure 6.1.1 shows the interrupt processing sequence. when an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses ffb4 16 to ffff 16 ). set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. 6.1 overview fig. 6.1.1 interrupt processing sequence interrupt routine interrupt request is accepted. processing is resumed. processing is suspended. returns to original routine. rti instruction interrupt processing routine in progress branches to start address of interrupt routine. [s] is an initial address that the stack pointer (s) indicates when an interrupt request is accepted. the s s contents become [s] 5 after all of the above registers are pushed. address [s] 4 [s] 3 [s] 2 [s] 1 [s] ? processor status register s low-order byte (ps l ) stack area [s] 5 processor status register s high-order byte (ps h ) program counter s low-order byte (pc l ) program counter s high-order byte (pc h ) program bank register (pg) ? fig. 6.1.2 state of stack area just before entering interrupt routine
7906 group user s manual rev.2.0 6-3 interrupts remarks non-maskable non-maskable software interrupt do not use. non-maskable internal interrupt do not use. maskable internal interrupts maskable internal interrupts maskable internal interrupts maskable internal interrupt maskable external interrupts do not use. non-maskable software interrupt do not use. maskable external interrupts 6.2 interrupt sources tables 6.2.1 and 6.2.2 list the interrupt sources and the interrupt vector addresses. when programming, set the start address of each interrupt routine to the vector addresses listed in these tables. 6.2 interrupt sources low-order address fffe 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 ffda 16 ffd8 16 ffd6 16 ffd4 16 ffd2 16 ffd0 16 ffce 16 ffcc 16 ffca 16 ffc8 16 ffc6 16 ffc4 16 ffc2 16 interrupt vector addresses table 6.2.1 interrupt sources and interrupt vector addresses (1) high-order address ffff 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffdb 16 ffd9 16 ffd7 16 ffd5 16 ffd3 16 ffd1 16 ffcf 16 ffcd 16 ffcb 16 ffc9 16 ffc7 16 ffc5 16 ffc3 16 interrupt source reset zero division brk instruction (note) dbc (note) watchdog timer reserved area reserved area reserved area reserved area timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 uart0 receive uart0 transmit uart1 receive uart1 transmit a-d conversion int 3 int 4 reserved area reserved area address matching detection reserved area int 5 int 6 int 7 note: the brk instruction and the dbc interrupt are used exclusively for a debugger. maskable interrupt: an interrupt of which request s acceptance can be disabled by software. non-maskable interrupt (including zero division, watchdog timer, and address matching detection interrupts) : an interrupt which is certain to be accepted when its request occurs. these interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (i). reference 3. reset 7900 series software manual 14. watchdog timer 7. timer a 8. timer b 11. serial i/o 12. a-d converter 6.10 external interrupts 17. debug function 6.10 external interrupts
7906 group user s manual rev.2.0 interrupts 6-4 remarks maskable internal interrupts do not use. low-order address ffc0 16 ffbe 16 ffbc 16 ffba 16 ffb8 16 ffb6 16 ffb4 16 interrupt vector addresses table 6.2.2 interrupt sources and interrupt vector addresses (2) high-order address ffc1 16 ffbf 16 ffbd 16 ffbb 16 ffb9 16 ffb7 16 ffb5 16 interrupt source timer a5 timer a6 timer a7 timer a8 timer a9 reserved area reserved area reference 7. timer a maskable interrupt: an interrupt of which request s acceptance can be disabled by software. 6.2 interrupt sources
7906 group user s manual rev.2.0 6-5 interrupts 6.3 interrupt control the maskable interrupts are controlled by the following : interrupt request bit interrupt priority level select bits processor interrupt priority level (ipl) interrupt disable flag (i) figure 6.3.1 shows the memory assignment of the interrupt control registers, and figures 6.3.2 shows their structures. } } assigned to an interrupt control register of each interrupt. assigned to the processor status register (ps). 6.3 interrupt control fig. 6.3.1 memory assignment of interrupt control registers 70 16 71 16 72 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 73 16 address 6f 16 6e 16 a-d conversion interrupt control register uart0 transmit interrupt control register uart1 transmit interrupt control register uart0 receive interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 4 interrupt control register int 3 interrupt control register f6 16 f7 16 f8 16 fd 16 fe 16 ff 16 f9 16 f5 16 timer a5 interrupt control register timer a6 interrupt control register timer a7 interrupt control register timer a8 interrupt control register timer a9 interrupt control register int 7 interrupt control register int 6 interrupt control register int 5 interrupt control register
7906 group user s manual rev.2.0 interrupts 6-6 fig. 6.3.2 structure of interrupt control register 6.3 interrupt control 0 1 2 3 7 to 4 a-d conversion, uart0 and 1 transmit, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 70 16 to 7c 16 ) timers a5 to a9 interrupt control registers (addresses f5 16 to f9 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt priority level select bits interrupt request bit nothing is assigned. notes 1: the a-d conversion interrupt request bit is undefined after reset. 2: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 0 0 0 (note 1) undefined rw rw rw rw (note 2) bit name bit function at reset r/w 0 1 2 3 4 5 7, 6 int 3 to int 7 interrupt control registers (addresses 6e 16 , 6f 16 , fd 16 , fe 16 , ff 16 ) interrupt priority level select bits interrupt request bit (note 1) polarity select bit level sense/edge sense select bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 notes 1: the interrupt request bits of int 3 to int 7 interrupts are invalid when the level sense is selected. 2: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 : the interrupt request bit is set to 1 at h level when level sense is selected; this bit is set to 1 at falling edge when edge sense is selected. 1 : the interrupt request bit is set to 1 at l level when level sense is selected; this bit is set to 1 at rising edge when edge sense is selected. 0 : edge sense 1 : level sense 0 0 0 0 0 0 undefined rw rw rw rw (note 2) rw rw bit name bit function at reset r/w
7906 group user s manual rev.2.0 6-7 interrupts 6.3.1 interrupt disable flag (i) all maskable interrupts can be disabled by this flag. when this flag is set to 1, all maskable interrupts are disabled; when this flag is cleared to 0, those interrupts are enabled. because this flag is set to 1 at reset, clear this flag to 0 when enabling interrupts. 6.3.2 interrupt request bit when an interrupt request occurs, this bit is set to 1. this bit remains set to 1 until the interrupt request is accepted; it is cleared to 0 when the interrupt request is accepted. this bit can also be set to 0 or 1 by software. the int i interrupt request bit (i = 3 to 7) is ignored when the corresponding int i interrupt is used with the level sense. 6.3.3 interrupt priority level select bits and processor interrupt priority level (ipl) the interrupt priority level select bits are used to determine the priority level of each interrupt. when an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when the comparison result meets the following condition. accordingly, any interrupt can be disabled by setting its interrupt priority level to 0. each interrupt priority level > processor interrupt priority level (ipl) table 6.3.1 lists the setting of interrupt priority levels, and table 6.3.2 lists the enabled interrupt s levels according to the ipl contents. the interrupt disable flag (i), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (ipl) are independent of one another; they do not affect one another. interrupt requests are accepted only when all of the following conditions are satisfied. interrupt disable flag (i) = 0 interrupt request bit = 1 interrupt priority level > processor interrupt priority level (ipl) 6.3 interrupt control
7906 group user s manual rev.2.0 interrupts 6-8 b0 0 1 0 1 0 1 0 1 b2 0 0 0 0 1 1 1 1 table 6.3.1 setting of interrupt priority level b1 0 0 1 1 0 0 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high 6.3 interrupt control interrupt priority level interrupt priority level select bits priority ipl 2 0 0 0 0 1 1 1 1 enabled interrupt s level level 1 and above are enabled. level 2 and above are enabled. level 3 and above are enabled. level 4 and above are enabled. level 5 and above are enabled. levels 6 and 7 are enabled. only level 7 is enabled. all maskable interrupts are disabled. ipl 1 0 0 1 1 0 0 1 1 ipl 0 0 1 0 1 0 1 0 1 table 6.3.2 enabled interrupt? levels according to ipl contents ipl 0 : bit 8 in processor status register (ps) ipl 1 : bit 9 in processor status register (ps) ipl 2 : bit 10 in processor status register (ps)
7906 group user s manual rev.2.0 6-9 interrupts 6.4 interrupt priority level when the interrupt disable flag (i) = 0 (interrupts enabled) and more than one interrupt request is detected at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they are accepted in descending sequence from the highest priority level. a maskable interrupt can be set to the desired priority level by using the interrupt priority level select bits. the priority levels of reset and a watchdog timer interrupt are set by hardware. figure 6.4.1 shows the interrupt priority levels set by hardware. note that software interrupts are not affected by the interrupt priority levels. whenever an instruction is executed, a branch is certainly made to the interrupt routine. 6.4 interrupt priority level fig. 6.4.1 interrupt priority levels set by hardware the user can set the desired priority level to a maskable interrupt. priority levels determined by hardware low high priority level reset watchdog timer maskable interrupts
7906 group user s manual rev.2.0 interrupts 6-10 6.5 interrupt priority level detection circuit the interrupt priority level detection circuit is used to select the interrupt with the highest priority level from multiple interrupt requests sampled at the same timing. figure 6.5.1 shows the interrupt priority level detection circuit. 6.5 interrupt priority level detection circuit fig. 6.5.1 interrupt priority level detection circuit ipl processor interrupt priority level interrupt with the highest priority level acceptance of interrupt request watchdog timer interrupt reset interrupt disable flag (i) level 0 (initial value) interrupt priority level a-d conversion int 4 int 3 timer a2 timer a1 timer a0 interrupt priority level timer a4 timer a3 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 int 6 int 5 int 7 timer a5 timer a6 timer a7 timer a8 timer a9
7906 group user s manual rev.2.0 6-11 interrupts the following explains the operation of the interrupt priority level detection circuit using figure 6.5.2. the interrupt priority level of a requested interrupt (y in figure 6.5.2) is compared with the resultant priority level which is sent from the preceding comparator (x in figure 6.5.2); the interrupt with the higher priority level will be sent to the next comparator (z in figure 6.5.2). (the initial value of the comparison level is 0. ) for an interrupt which is not requested, the comparison is not performed, and the priority level which is sent from the preceding comparator is sent to the next comparator as it is. when the two priority levels are found the same, as a resultant of the comparison, the priority level which is sent from the preceding comparator will be sent to the next comparator. accordingly, when the same priority level is set to multiple interrupts by software, their interrupt priority levels are handled as follows: timer a9 > timer a8 > timer a7 > timer a6 > timer a5 > int 7 > int 6 > int 5 > int 4 > int 3 > a-d conversion > uart1 transmit > uart1 receive > uart0 transmit > uart0 receive > timer b2 > timer b1 > timer b0 > timer a4 > timer a3 > timer a2 > timer a1 > timer a0 among the multiple interrupt requests sampled at the same timing, one request with the highest priority level is detected by the above comparison. then, this highest interrupt priority level is compared with the processor interrupt priority level (ipl). when this interrupt priority level is higher than ipl and the interrupt disable flag (i) is 0, the interrupt request is accepted. an interrupt request which is not accepted here is retained until it is accepted or its interrupt request bit is cleared to 0 by software. the interrupt priority level is detected when the cpu fetches an op code, which is called the cpu s op-code fetch cycle. however, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt priority detection does not start. (see figure 6.6.2.) since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt priority detection is performed for the state just before the change occurs. the interrupt priority level is detected when the cpu fetches an op code. therefore, in the following case, no interrupt request is accepted until the cpu fetches the op code of the next instruction after the following operation is completed: execution of an instruction which requires many cycles, such as the mvn and mvp instructions 6.5 interrupt priority level detection circuit y x z comparator (priority level comparison) when x y then z = x when x < y then z = y interrupt source y x : priority level sent from the preceding comparator (highest priority level at this point) y : priority level of interrupt source y z : highest priority level at this point time fig. 6.5.2 interrupt priority level detection model
7906 group user? manual rev.2.0 interrupts 6-12 6.6 interrupt priority level detection time when the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. the interrupt priority level detection time can be selected by software. (see figure 6.6.1.) usually, select ? cycles of f sys ?as the interrupt priority level detection time. figure 6.6.2 shows the interrupt priority level detection time. 6.6 interrupt priority level detection time fig. 6.6.2 interrupt priority level detection time f sys op-code fetch cycle sampling pulse (a) 7 cycles of f sys (b) 4 cycles of f sys (c) 2 cycles of f sys interrupt priority level detection time (note) note: the p ulse resides when 2 c y cles of f s y s is selected. fig. 6.6.1 structure of processor mode register 0 0 1 2 3 4 5 6 7 bit name bit processor mode register 0 (address 5e 16 ) function at reset r/w processor mode bits interrupt priority detection time select bits software reset bit fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 0 : single-chip mode 0 1 : do not select. 1 0 : do not select. 1 1 : do not select. b1 b0 0 0 : 7 cycles of f sys 0 1 : 4 cycles of f sys 1 0 : 2 cycles of f sys 1 1 : do not select. b5 b4 the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 0 1 0 0 0 0 rw rw rw rw rw rw wo rw 0xx 0 0 any of these bits may be either 0 or 1. x : it may be either 0 or 1.
7906 group user s manual rev.2.0 interrupts 6-13 6.7 sequence from acceptance of interrupt request until execution of interrupt routine the sequence from acceptance of an interrupt request until execution of the interrupt routine is described below. when an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to 0. and then, the interrupt processing starts from the cycle just after completion of the instruction execution which was executed at acceptance of the interrupt request. figure 6.7.1 shows the sequence from occurrence of an interrupt request until execution of the interrupt routine. after execution of an instruction at acceptance of the interrupt request is completed, an intack (interrupt acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 to ffff 16 . in the intack sequence, the following are automatically performed in ascending sequence from ? to ? . ? the contents of the program bank register (pg) just before performing the intack sequence are pushed onto stack. ? the contents of the program counter (pc) just before performing the intack sequence are pushed onto stack. ? the contents of the processor status register (ps) just before performing the intack sequence is pushed onto stack. ? the interrupt disable flag (i) is set to 1. ? the interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (ipl). ? the contents of the program bank register (pg) are cleared to 00 16 , and the contents of the interrupt vector address are set into the program counter (pc). performing the intack sequence requires at least 15 cycles of f sys . figure 6.7.2 shows the intack sequence timing. after the intack sequence is completed, the instruction execution starts from the start address of the interrupt routine. 6.7 sequence from acceptance of interrupt request until execution of interrupt routine @ @ : interrupt priority level detection time interrupt request occurs. interrupt request is accepted. instruction 1 instruction 2 intack sequence instructions in interrupt routine interrupt response time time @ ? time from occurrence of an interrupt request until comparison of an instruction execution which is in progress at that time. ? time from execution start of an instruction next to ? until completion of execution of the instruction which was in progress at detection completed. ? time required to perform the intack sequence (15 cycles of at minimum) ? ? ? fig. 6.7.1 sequence from occurrence of interrupt request until execution of interrupt routine
7906 group user s manual rev.2.0 interrupts 6-14 6.7 sequence from acceptance of interrupt request until execution of interrupt routine fig. 6.7.2 intack sequence timing (at minimum) 6.7.1 change in ipl at acceptance of interrupt request when an interrupt request is accepted, the processor interrupt priority level (ipl) is replaced with the interrupt priority level of the accepted interrupt. this results in easy control of the processing for multiple interrupts. (refer to section ?.9 multiple interrupts. ) at acceptance of a watchdog timer interrupt request, a zero division request, or address matching detection interrupt request or at reset, a value in table 6.7.1 is set into the ipl. table 6.7.1 change in ipl at acceptance of interrupt request interrupts reset watchdog timer zero division address matching detection other interrupts change in ipl level 0 ( 000 2 ) is set. level 7 ( 111 2 ) is set. not changed. not changed. accepted interrupt s priority level is set. when stack pointer (s) s contents are even at acceptance of an interrupt request with bus cycle = 2 undefined 00 00 00 00 00 ad 23 ad 16 blw bhw f sys rd 00 intack sequence cpu [s]: contents of stack pointer (s) ffxx 16 : vector address f sys , cpu : internal clock (see figure 4.2.1.) ad 23 ad 0 : internal address bus db 15 db 0 : internal data bus ad 15 ad 0 db 15 db 8 db 7 db 0 undefined 0000 [s] 2 [s] 4 ffxx 16 ad 15 ad 0 [s] undefined ipl pc h ps h ad 15 ad 8 next instruction undefined (low-order) pc l ps l ad 7 ad 0 next instruction pg note: these are internal signals and are not output to the external. vector address (note) (note) (note) (note) (note) (note) (note) (note)
7906 group user s manual rev.2.0 interrupts 6-15 6.7.2 push operation for registers the push operation for registers performed in the intack sequence depends on whether the contents of the stack pointer (s) at acceptance of an interrupt request are even or odd. when the contents of the stack pointer (s) are even, the contents of the program counter (pc) and the processor status register (ps) are simultaneously pushed in a unit of 16 bits. when the contents of the stack pointer (s) are odd, each of pc and ps is pushed in a unit of 8 bits. figure 6.7.3 shows the push operation for registers. in the intack sequence, only the contents of the program bank register (pg), program counter (pc), and processor status register (ps) are pushed onto the stack area. other necessary registers must be pushed by software at the start of the interrupt routine. by using the psh instruction, all cpu registers, except the stack pointer (s), can be pushed with 1 instruction. 6.7 sequence from acceptance of interrupt request until execution of interrupt routine fig. 6.7.3 push operation for registers pushed in 3 times. ? pushed in a unit of 16 bits. ? ? pushed in a unit of 16 bits. (1) when contents of stack pointer (s) are even program bank register (pg) address [s] 4 (even) [s] 3 (odd) [s] 2 (even) [s] 1 (odd) [s] (even) order for push [s] 5 (odd) address [s] 4 (odd) [s] 3 (even) [s] 2 (odd) [s] 1 (even) [s] (odd) ? ? ? ? ? pushed in a unit of 8 bits. order for push pushed in 5 times. [s] 5 (even) low-order byte of program counter (pc l ) high-order byte of program counter (pc h ) (2) when contents of stack pointer (s) are odd low-order byte of processor status register (ps l ) program bank register (pg) high-order byte of processor status register (ps h ) low-order byte of program counter (pc l ) high-order byte of program counter (pc h ) ? [s] is the initial address that the stack pointer (s) indicates at acceptance of an interrupt request. the s s contents become [s] 5 after all of the above registers are pushed. low-order byte of processor status register (ps l ) high-order byte of processor status register (ps h )
7906 group user s manual rev.2.0 interrupts 6-16 6.8 return from interrupt routine when the rti instruction is executed at the end of the interrupt routine, the contents of the program bank register (pg), program counter (pc), and processor status register (ps) which were pushed onto the stack area just before the intack sequence are automatically pulled. after this, the control returns to the original routine. and then, the suspended processing, which was in progress before acceptance of the interrupt request, is resumed. before the rti instruction is executed, registers which were pushed by software in the interrupt routine must be pulled in the same data length and register length as those in pushing, using the pul instruction, etc. 6.9 multiple interrupts just after a branch is made to an interrupt routine, the following occur: interrupt disable flag (i) = 1 (interrupts are disabled.) interrupt request bit of accepted interrupt = 0 processor interrupt priority level (ipl) = interrupt priority level of accepted interrupt accordingly, as long as the ipl remains unchanged, an interrupt request, whose priority level is higher than that of the interrupt which is in progress, can be accepted by clearing the interrupt disable flag (i) to 0 in an interrupt routine. in this way, multiple interrupts are processed. figure 6.9.1 shows the processing for multiple interrupts. an interrupt request which has not been accepted because its priority level is lower is retained. when the rti instruction is executed, the interrupt priority level of the routine which was in progress just before acceptance of an interrupt request is pulled into the ipl. therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the retained interrupt request will be accepted. retained interrupt request s priority level > processor interrupt priority level (ipl) note: when any of the following interrupt requests is generated while an interrupt routine is in progress, this interrupt request is accepted at once: zero division, watchdog timer, and address matching detection. 6.8 return from interrupt routine, 6.9 multiple interrupts
7906 group user s manual rev.2.0 interrupts 6-17 6.9 multiple interrupts fig. 6.9.1 processing for multiple interrupts interrupt priority level = 2 main routine reset i = 1 ipl = 0 i = 0 interrupt 1 i = 1 ipl = 3 i = 0 i = 1 ipl = 5 rti i = 0 ipl = 3 rti i = 0 ipl = 0 i = 1 ipl = 2 rti i = 0 ipl = 0 interrupt 1 interrupt priority level = 3 this request cannot be accepted because its priority level is lower than the interrupt 1 s one. interrupt request generated nesting time : they are automatically executed. : they must be set by software. i : interrupt disable flag ipl : processor interrupt priority level multiple interrupts interrupt 2 interrupt priority level = 5 interrupt 3 interrupt 2 interrupt 3 interrupt 3 the instruction in the main routine is not executed.
7906 group user s manual rev.2.0 interrupts 6-18 level sense/edge sense select bit (bit 5 at addresses 6e 16 , 6f 16 , fd 16 to ff 16 ) 0 0 1 1 6.10 external interrupts the external interrupts consist of int i interrupts. 6.10.1 int i interrupt an int i (i = 3 to 7) interrupt request occurs by an input signal to pin int i . table 6.10.1 lists the occurrence factor of the int i interrupt request. the allocation of pin int 3 can be changed by the pin int 3 /rtp trg0 select bit. (see figure 6.10.1.) when using any of pins p7 4 (p2 7 )/int 3 , p5 5 /int 5 , p5 6 /int 6 , p5 7 /int 7 as an input pin of the external interrupt, be sure to clear the port direction register s bit corresponding to the above pin. (see figure 6.10.3.) when using pin p6out cut /int 4 as an input pin of an external interrupt (pin int 4 ), be sure to use port pins p6 0 to p6 5 in the input mode. (refer to section 5.2.3 pin p6out cut /int 4 . ) the signal input to pin int i requires h or l level width of 250 ns or more, independent of f(x in ). by reading out the int i read bit (see figure 6.10.2.), the state of pin int i can be read out. note: selection of the interrupt occurrence factor requires the following conditions: when an input signal s falling edge or l level is selected, be sure that l level width 250 ns. when an input signal s rising edge or h level is selected, be sure that h level width 250 ns. 6.10 external interrupts table 6.10.1 occurrence factor of int i interrupt request polarity select bit (bit 4 at addresses 6e 16 , 6f 16 , fd 16 to ff 16 ) 0 1 0 1 the int i interrupt request occurs by detecting the state of pin int i all the time. therefore, when the user does not use an int i interrupt, be sure to set the int i interrupt s priority level to 0. int 3 to int 7 occurrence factor of interrupt request (an interrupt request occurs when the input signal of pin int i is as follows.) falling edge (edge sense) rising edge (edge sense) h level (level sense) l level (level sense)
7906 group user s manual rev.2.0 interrupts 6-19 6.10 external interrupts fig. 6.10.1 structure of port p2 pin function control register fig. 6.10.2 structure of external interrupt input read register port p2 pin function control register (address ae 16 ) 0 1 2 3 6 to 4 7 bit name bit function at reset r/w pin tb0 in select bit pin tb1 in select bit pin tb2 in select bit pin int 3 /rtp trg0 select bit (note) nothing is assigned. fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 : allocate pin tb2 in to p5 7 . 1 : allocate pin tb2 in to p2 6 . 0: allocate pin int 3 /rtp trg0 to p7 4 . 1: allocate pin int 3 /rtp trg0 to p2 7 . 0 : allocate pin tb0 in to p5 5 . 1 : allocate pin tb0 in to p2 4 . 0 : allocate pin tb1 in to p5 6 . 1 : allocate pin tb1 in to p2 5 . 0 0 0 0 undefined 0 rw rw rw rw rw note: when allocating pin int 3 /rtp trg0 to p7 4 , be sure the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 0 2 to 0 3 4 5 6 7 bit name bit function at reset r/w external interrupt input read register (address 95 16 ) the value is undefined at reading. int 3 read out bit int 4 read out bit int 5 read out bit int 6 read out bit int 7 read out bit undefined undefined undefined undefined undefined undefined ro ro ro ro ro ro b7 b6 b5 b4 b3 b2 b1 b0 the input level at the corresponding pin is read out. 0 : l level 1 : h level
7906 group user s manual rev.2.0 interrupts 6-20 fig. 6.10.3 relationship between port p2/p5/p7 direction register and external interrupt s input pins 6.10 external interrupts corresponding pin bit 0 1 2 3 4 5 6 7 port p2 direction register (address 8 16 ) function at reset r/w pin ta4 out pin ta4 in pin ta9 out pin ta9 in pin tb0 in (note 1) pin tb1 in (note 2) pin tb2 in (note 3) pin int 3 (rtp trg0 ) (note 4) 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 notes 1: this applies when the pin tb0 in select bit (bit 0 at address ae 16 ) = 1. 2: this applies when the pin tb1 in select bit (bit 1 at address ae 16 ) = 1. 3: this applies when the pin tb2 in select bit (bit 2 at address ae 16 ) = 1. 4: this applies when the pin int 3 /rtp trg0 select bit (bit 3 at address ae 16 ) = 1. 5: ( ) shows the i/o pins of other internal peripheral device which are multiplexed. 0 : input mode 1 : output mode when using this pin as an external interrupt s input pin, be sure to clear the corresponding bit to 0. corresponding pin bit 4 to 0 5 6 7 port p5 direction register (address d 16 ) function at reset r/w nothing is assigned. pin int 5 (tb0 in /idw) pin int 6 (tb1 in /idv) pin int 7 (tb2 in /idu) rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 note: ( ) shows the i/o pins of other internal peripheral devices which are multiplexed. 0 : input mode 1 : output mode when using this pin as an external interrupt s input pin, be sure to clear the corresponding bit to 0. corresponding pin bit 0 1 2 3 4 7 to 5 port p7 direction register (address 11 16 ) function at reset r/w 0 0 0 0 0 undefined rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 notes 1: this applies when the pin int 3 /rtp trg0 select bit (bit 3 at address ae 16 ) = 0. 2: ( ) shows the i/o pins of other internal peripheral devices which are multiplexed. 0 : input mode 1 : output mode when using this pin as an external interrupt s input pin, be sure to clear the corresponding bit to 0. pin an 0 pin an 1 pin an 2 pin an 3 /da 0 pin int 3 (an 4 /da 1 /rtp trg0 ) (note 1) nothing is assigned. undefined 0 0 0
7906 group user s manual rev.2.0 interrupts 6-21 6.10 external interrupts 6.10.2 functions of int i interrupt request bit figure 6.10.4 shows an int i interrupt request. (1) functions when edge sense is selected in this case, the interrupt request bit has the same function as that of an internal interrupt. that is, when an interrupt request occurs, the interrupt request bit is set to 1 and retains this state until the interrupt request is accepted. when this bit is cleared to 0 by software, the interrupt request is cancelled; when this bit is set to 1 by software, the interrupt request can occur. (2) functions when level sense is selected in this case, the interrupt request bit is ignored. int i interrupt requests continuously occur while the level at pin int i is the valid level ? 1 ; when the level at pin int i changes from the valid level to the invalid level ? 2 before the corresponding int i interrupt request is accepted, this interrupt request is not retained. (see figure 6.10.5.) valid level ? 1 : this means the level selected by the polarity select bit (bit 4 at addresses 6e 16 , 6f 16 , fd 16 to ff 16 ) invalid level ? 2 : this means the reversed level of valid level data bus edge detection circuit interrupt request 0 1 interrupt request bit pin int i level sense/edge sense select bit fig. 6.10.4 int i interrupt request fig. 6.10.5 occurrence of int i interrupt request when level sense is selected when the level at pin int i changes to the invalid level before the int i interrupt request is accepted, this interrupt request is not retained. first interrupt routine level at pin int i valid invalid main routine interrupt request is accepted. return to main routine. second interrupt routine third interrupt routine main routine
7906 group user s manual rev.2.0 interrupts 6-22 6.10 external interrupts 6.10.3 switching of int i to interrupt request occurrence factor when the int i interrupt request occurrence factor is switched in one of the following ways, there is a possibility that the corresponding interrupt request bit is set to 1 : switching the factor from the level sense to the edge sense switching the polarity therefore, after this switching, make sure to clear the corresponding interrupt request bit to 0. figure 6.10.6 shows an example of the switching procedure for the int i interrupt request s occurrence factor. fig. 6.10.6 example of switching procedure for int i interrupt request s occurrence factor set the interrupt priority level to one of levels 1 7 or clear the interrupt disable flag (i) to 0. (int i interrupt request is acceptable.) set the interrupt priority level to one of levels 1 7 or clear the interrupt disable flag (i) to 0. (int i interrupt request is acceptable.) clear the level sense/edge sense select bit to 0. (edge sense is selected.) clear the interrupt request bit to 0. set the polarity select bit. clear the interrupt request bit to 0. (2) switching the polarity (1) switching the factor from the level sense to the edge sense set the interrupt priority level to 0 or set the interrupt disable flag (i) to 1. (int i interrupt is disabled.) note: the above settings must be done separately. multiple settings must not be done at the same time, in other words, they must not be done only by 1 instruction. set the interrupt priority level to 0 or set the interrupt disable flag (i) to 1. (int i interrupt is disabled.)
7906 group user s manual rev.2.0 interrupts 6-23 b4 0 1 0 1 fig. 6.10.7 program example to reserve time required for change of interrupt priority level table 6.10.2 correspondence between number of instructions to be inserted in figure 6.10.7 and interrupt priority detection time select bits [precautions for interrupts] [precautions for interrupts] 1. in order to change the interrupt priority level select bits (bits 0 to 2 at addresses 6e 16 to 7c 16 , f5 16 to f9 16 , fd 16 to ff 16 ), 2 to 7 cycles of f sys are required after execution of a write instruction until change of the interrupt priority level. therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions, it is necessary to reserve the time required for the change by software. figure 6.10.7 shows a program example to reserve the time required for the change. note that the time required for the change depends on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5e 16 ). table 6.10.2 lists the correspondence between the number of instructions inserted in figure 6.10.7 and the interrupt priority detection time select bits. interrupt priority detection time select bits (note) interrupt priority level detection time 7 cycles of f sys 4 cycles of f sys 2 cycles of f sys do not select. b5 0 0 1 1 number of inserted nop instructions 7 or more 4 or more 2 or more note: we recommend [b5 = 1 , b4 = 0 ]. 2. when allocating pin int 3 to pin p7 4 , be sure that the d-a 1 output enable bit (bit 2 at address 96 16 ) = 0 (output disabled). 3. when using pin p6out cut /int 4 as an input pin of an external interrupt (pin int 4 ), be sure to use port pins p6 0 to p6 5 in the input mode. (refer to section 5.2.3 pin p6out cut /int 4 . ) ; write instruction for the interrupt priority level select bits ; inserted nop instruction (note) ; ; ; write instruction for the interrupt priority level select bits note: except a write instruction for address xx 16 , any instruction which has the same cycles as the nop instruction can also be inserted, instead of the nop instruction. for the number of inserted nop instructions, see table 6.10.2. xx: any of 6e to 7f, f1, f2, f5 to f9, and fd to ff : movmb 00xxh, #0xh nop nop nop movmb 00xxh, #0xh :
7906 group user s manual rev.2.0 interrupts 6-24 [precautions for interrupts] memorandum
chapter 7 timer a 7.1 overview 7.2 block description 7.3 timer mode [precautions for timer mode] 7.4 event counter mode [precautions for event counter mode] 7.5 one-shot pulse mode [precautions for one-shot pulse mode] 7.6 pulse width modulation (pwm) mode [precautions for pulse width modulation (pwm) mode]
timer a 7906 group user? manual rev.2.0 7-2 7.1 overview timer a consists of ten counters, timers a0 to a9, each equipped with a 16-bit reload function. timers a0 to a9 operate independently of one other. each timer is equipped with the different operating mode; therefore, in this chapter, timers are referred to as follows: ?timers a0 to a9; timer ai ( i = 0 to 9) ?timer a, equipped with the i/o function; timer aj (j = 0 to 2, 4, 9) ?timer a, not equipped with the i/o function; timer ak (k = 3, 5 to 8) timer aj (j = 0 to 2, 4, 9) has four operating modes listed below. except for the event counter mode, timer aj has the same functions. timer ak (k = 3, 5 to 8) is equipped with the timer mode only. table 7.1.1 lists the functions of timer ai (i = 0 to 9). (1) timer mode : timer ai (i = 0 to 9) in this mode, the timer counts an internally generated count source. for timer aj (j = 0 to 2, 4, 9), following functions can be used in this mode: ?gate function ?pulse output function (2) event counter mode : timer aj (j = 0 to 2, 4, 9) in this mode, the timer counts an external signal. following functions can be used in this mode: ?pulse output function ?two-phase pulse signal processing function (timers a2, a4, and a9) (3) one-shot pulse mode : timer aj (j = 0 to 2, 4, 9) in this mode, the timer outputs a pulse which has an arbitrary width once. (4) pulse width modulation (pwm) mode : timer aj (j = 0 to 2, 4, 9) in this mode, the timer outputs pulses which have an arbitrary width in succession. in this mode, the timer serves as one of the following pulse width modulators: ?16-bit pulse width modulator ?8-bit pulse width modulator 7.1 overview
timer a 7906 group user? manual rev.2.0 7-3 timer mode event counter mode one-shot pulse mode pulse width modulation (pwm) mode functions of timers timer gate function pulse output function pulse output function two-phase pulse signal processing function timer ai (i = 0 to 9) timer aj (j = 0 to 2, 4 ,9) timer ak (k = 3, 5 to 8) ta0 ta1 ta2 ta4 ta9 ta3 ta5 ta6 ta7 ta8 (note) note: normal processing for ta2; and quadruple processing for ta4, ta9 table 7.1.1 functions of timer ai (i = 0 to 9) 7.1 overview
timer a 7906 group user? manual rev.2.0 7-4 7.2 block description figure 7.2.1 shows the block diagram of timer aj (j = 0 to 2, 4, 9). figure 7.2.2 shows the block diagram of timer ak (k = 3, 5 to 8). explanation of registers relevant to timer a is described below. 7.2 block description fig. 7.2.1 block diagram of timer aj (j = 0 to 2, 4, 9) data bus (odd) data bus (even) f 2 f 16 f 512 count source select bit timer mode one-shot pulse mode pwm mode polarity switching timer mode (gate function) event counter mode trigger count start bit countdown up-down bit (low-order 8 bits) (high-order 8 bits) timer aj reload register (16) timer aj counter (16) timer aj interrupt request bit countup/countdown switching (always countdown except for in the event counter mode) toggle f.f. pulse output function select bit taj in taj out note: common to timers a0 to a9. f 64 f 1 f 4096 timer a clock division select bits (note) fig. 7.2.2 block diagram of timer ak (k = 3, 5 to 8) data bus (odd) data bus (even) timer mode count start bit (low-order 8 bits) (high-order 8 bits) timer ak reload register (16) timer ak counter (16) timer ak interrupt request bit f 4096 count source select bit f 2 f 16 f 512 f 1 f 64 timer a clock division select bits (note) note: common to timers a0 to a9.
timer a 7906 group user s manual rev.2.0 7-5 timer ai register high-order byte low-order byte timer a0 register address 47 16 address 46 16 timer a1 register address 49 16 address 48 16 timer a2 register address 4b 16 address 4a 16 timer a3 register address 4d 16 address 4c 16 timer a4 register address 4f 16 address 4e 16 timer a5 register address c7 16 address c6 16 timer a6 register address c9 16 address c8 16 timer a7 register address cb 16 address ca 16 timer a8 register address cd 16 address cc 16 timer a9 register address cf 16 address ce 16 7.2.1 counter and reload register (timer ai register) each of timer ai counter and reload register consists of 16 bits. countdown in the counter is performed each time the count source is input. in the event counter mode, it can also function as an up-counter. the reload register is used to store the initial value of the counter. when a counter underflow or overflow occurs, the reload register s contents are reloaded into the counter. a value is set to the counter and reload register by writing the value to the timer ai register. table 7.2.1 lists the memory assignment of the timer ai register. the value written into the timer ai register while counting is not in progress is set to the counter and reload register. the value written into the timer ai register while counting is in progress is set only to the reload register. in this case, the reload register s updated contents are transferred to the counter at the next reload time. the value obtained when reading out the timer ai register varies according to the operating mode. table 7.2.2 lists reading from and writing to the timer ai register. 7.2 block description table 7.2.2 reading from and writing to timer ai register write written only to reload register. written to both of the counter and reload register. operating mode timer mode event counter mode one-shot pulse mode pulse width modulation (pwm) mode note: at reset, the contents of the timer ai register are undefined. notes 1: also refer to sections ?precautions for timer mode] and ?precautions for event counter mode]. 2: when reading from and writing to the timer ai register, perform it in a unit of 16 bits. 3: each of timers a3 and a5 to a8 is equipped with the timer mode only. read counter value is read out. ( note 1 ) undefined value is read out. table 7.2.1 memory assignment of timer ai register
timer a 7906 group user s manual rev.2.0 7-6 7.2.2 timer a clock division select register in the timer mode, one-shot pulse mode, and pulse width modulation (pwm) mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5a 16 , d6 16 to da 16 ), and timer a clock division select bits (bits 0 and 1 at address 45 16 ) select the count source. figure 7.2.3 shows the structure of the timer a clock division select register. table 7.2.3 lists the count source (in the timer mode, one-shot pulse mode, and pulse width modulation (pwm) mode). each of timers a3 and a5 to a8 is equipped with the timer mode only. 7.2 block description fig. 7.2.3 structure of timer a clock division select register table 7.2.3 count source (in timer mode, one-shot pulse mode, and pulse width modulation (pwm) mode) count source select bits (bits 6 and 7 at addresses 56 16 to 5a 16 , d6 16 to da 16 ) 00 01 10 11 00 f 2 f 16 f 64 f 512 01 f 1 f 16 f 64 f 4096 10 f 1 f 64 f 512 f 4096 11 do not select. timer a clock division select bits (bits 0 and 1 at address 45 16 ) 0 1 7 to 2 timer a clock division select register (address 45 16 ) timer a clock division select bits the value is 0 at reading. 0 0 0 rw rw b7 b6 b5 b4 b3 b2 b1 b0 see table 7.2.3. bit name bit function at reset r/w
timer a 7906 group user s manual rev.2.0 7-7 7.2.3 count start register this register is used to start and stop counting. one bit of this registar corresponds to one timer. (this is the one-to-one relationship.) figure 7.2.4 shows the structures of the count start registers 0 and 1. 7.2 block description 0 1 2 3 4 5 6 7 count start register 0 (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : stop counting 1 : start counting bit name bit function at reset r/w fig. 7.2.4 structures of count start registers 0 and 1 0 0 0 0 0 undefined 0 1 2 3 4 7 to 5 count start register 1 (address 41 16 ) timer a5 count start bit timer a6 count start bit timer a7 count start bit timer a8 count start bit timer a9 count start bit nothing is assigned. rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : stop counting 1 : start counting bit name bit function at reset r/w
timer a 7906 group user s manual rev.2.0 7-8 7.2.4 timer ai mode register figure 7.2.5 shows the structure of the timer ai mode register. the operating mode select bits are used to select the operating mode of timer ai. bits 2 to 7 have different functions according to the operating mode. these bits are described in the paragraph of each operating mode. fig. 7.2.5 structure of timer ai mode register operating mode select bits (note) these bits have different functions according to the operating mode. 0 1 2 3 4 5 6 7 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) (i = 5 to 9) (addresses d6 16 to da 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot pulse mode 1 1 : pulse width modulation (pwm) mode b1 b0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw bit name bit function at reset r/w note: in timers a3 and a5 to a8, fix these bits to 00 2 . do not select 01 2 , 10 2 , and 11 2 . 7.2 block description
timer a 7906 group user s manual rev.2.0 7-9 7.2.5 timer ai interrupt control register figure 7.2.6 shows the structure of the timer ai interrupt control register. for details about interrupts, refer to ?hapter 6. interrupts. 7.2 block description b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 7 to 4 interrupt priority level select bits interrupt request bit nothing is assigned. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 0 0 0 undefined rw rw rw rw (note) bit name bit function at reset r/w timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) (i = 5 to 9) (addresses f5 16 to f9 16 ) note: when writing to this bit, use the movm (movmb) instruction or sta (stab, stad) instruction. fig. 7.2.6 structure of timer ai interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits are used to select a timer ai interrupt s priority level. when using timer ai interrupts, select the priority level from levels 1 through 7. when a timer ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl), so that the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0. ) to disable timer ai interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a timer ai interrupt request occurs. this bit is automatically cleared to 0 when the timer ai interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software.
timer a 7906 group user s manual rev.2.0 7-10 rw rw rw rw rw rw 0 1 2 3 4 5 7, 6 0 0 0 0 0 0 0 0 pin ta4 out pin ta4 in pin ta9 out pin ta9 in pin tb0 in (note 1) pin tb1 in (note 2) pin tb2 in (note 3) pin int 3 /rtp trg0 (note 4) 7.2 block description 7.2.6 port p2 and port p6 direction registers the i/o pins of timers a0 to a2 are multiplexed with port p6 pins, and the i/o pins of timers a4 and a9 are multiplexed with port p2 pins. when using these pins as timer aj (j = 0 to 2, 4, 9) s input pins, clear the corresponding bits of the port p6 and port p2 direction registers to 0 in order to set these port pins for the input mode. when used as timer aj s output pins, these pins are forcibly set to the output pins of timer aj regardless of the direction registers contents. figure 7.2.7 shows the relationship between the port p6 and port p2 direction registers and the timer aj s i/o pins. note that each bit of the port p6 direction register becomes 0 by an input of a falling edge to pin p6out cut . (refer to section ?.2.3 pin p6out cut /int 4 . ) when switching the output pins of timers a0 to a2 to the port output pins, the following procedure is required. ? return the input level at pin p6out cut to h. write data to the port p6 register s bit corresponding to the port p6 pin, where data is to be output. ? set 1 to the port p6 direction register s bit corresponding to the above p6 register s bit; therefore, this bit enters the output mode. when the input level at pin p6out cut = l, no bit of the port p6 direction register can be set to 1. fig. 7.2.7 relationship between port p6 and port p2 direction registers and timer aj? i/o pins 0 1 2 3 4 5 6 7 port p2 direction register (address 8 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode 1 : output mode when using this pin as timer aj s input pin, be sure to clear the corresponding bit to 0. rw rw rw rw rw rw rw rw corresponding pin bit functions at reset r/w notes 1: this applies when the tb0 in pin select bit (bit 0 at address ae 16 ) = 1. 2: this applies when the tb1 in pin select bit (bit 1 at address ae 16 ) = 1. 3: this applies when the tb2 in pin select bit (bit 2 at address ae 16 ) = 1. 4: this applies when the int 3 /rtp trg0 pin select bit (bit 3 at address ae 16 ) = 1. 5: the pins in ( ) are i/o pins of other internal peripheral devices, which are multiplexed. port p6 direction register (address 10 16 ) pin ta0 out (pin w/rtp0 0 ) pin ta0 in (pin v/rtp0 1 ) pin ta1 out (pin u/rtp0 2 ) pin ta1 in (pin w/rtp0 3 ) pin ta2 out (pin v/rtp1 0 ) pin ta2 in (pin u/rtp1 1 ) nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode 1 : output mode when using this pin as timer aj s input pin, be sure to clear the corresponding bit to 0. 0 0 0 0 0 0 undefined corresponding pin bit functions at reset r/w notes 1: each of bits 0 to 5 becomes 0 by an input of the falling edge to pin p6out cut /int 4 . (refer to section ?.2.3 pin p6out cut / int 4 . ) 2: the pins in ( ) are i/o pins of other internal peripheral devices, which are multiplexed.
timer a 7906 group user s manual rev.2.0 7-11 7.3 timer mode in this mode, the timer counts an internally generated count source. table 7.3.1 lists the specifications of the timer mode. figure 7.3.1 shows the structures of the timer ai register and timer ai mode register in the timer mode. table 7.3.1 specifications of timer mode item count source f i count operation division ratio count start condition count stop condition interrupt request occurrence timing taj in pin function taj out pin function read from timer ai register write to timer ai register specifications f 1 , f 2 , f 16 , f 64 , f 512 , or f 4096 countdown when a counter underflow occurs, reload register s contents are reloaded, and counting continues. when count start bit is set to 1. when count start bit is cleared to 0. when a counter underflow occurs. programmable i/o port pin or gate input pin programmable i/o port pin or pulse output pin counter value can be read out. while counting is stopped when a value is written to the timer ai register, it is written to both reload register and counter. while counting is in progress when a value is written to the timer ai register, it is written to only reload register. (transferred to the counter at the next reload timing.) n : timer ai register setting value 1 (n + 1) 7.3 timer mode note: only timer aj (j = 0 to 2, 4, 9) is equipped with the i/o pins.
timer a 7906 group user s manual rev.2.0 7-12 7.3 timer mode fig. 7.3.1 structures of timer ai register and timer ai mode register in timer mode 0 1 2 3 4 5 6 7 timer a0 register (addresses 47 16 , 46 16 ) timer a5 register (addresses c7 16 , c6 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a6 register (addresses c9 16 , c8 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a7 register (addresses cb 16 , ca 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a8 register (addresses cd 16 , cc 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined 15 to 0 any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. rw b0 b7 b0 b7 (b15) (b8) timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits pulse output function select bit gate function select bits fix this bit to 0 in timer mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 00 0 0 : no gate function 0 1 : (taj in pin functions as a programmable i/o port pin.) 1 0 : gate function (counter is active only while taj in pin s in- put signal is at l level.) 1 1 : gate function (counter is active only while taj in pin s in- put signal is at h level.) b4 b3 0 : no pulse output (taj out pin functions as a programmable i/o port pin.) 1 : pulse output (taj out pin functions as a pulse output pin.) 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw see table 7.2.3. 0 bit name bit function at reset r/w bit function at reset r/w 0 1 5 to 2 6 7 timer ak mode register (k = 3, 5 to 8) (addresses 59 16 , d6 16 to d9 16 ) operating mode select bits fix these bits to 0000 in timer mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 00 0 0 0 0 0 rw rw rw rw rw see table 7.2.3. 0 bit name bit function at reset r/w 00 0
timer a 7906 group user s manual rev.2.0 7-13 7.3.1 setting for timer mode figure 7.3.2 shows an initial setting example for registers related to the timer mode. note that when using interrupts, set up to enable the interrupts. for details, refer to section ?hapter 6. interrupts. 7.3 timer mode fig. 7.3.2 initial setting example for registers relevant to timer mode note: counter divides the count source frequency by (n + 1). aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa b7 b0 pulse output function select bit (note) 0 : no pulse output 1 : pulses output 00 selecting timer mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) (i = 5 to 9) (addresses d6 16 to da 16 ) 1 0 : gate function (counter counts only while taj in pin s input signal level is l. ) 1 1 : gate function (counter counts only while taj in pin s input signal level is h. ) b4 b3 selection of timer mode aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa setting division ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a5 register (addresses c7 16 , c6 16 ) timer a6 register (addresses c9 16 , c8 16 ) timer a7 register (addresses cb 16 , ca 16 ) timer a8 register (addresses cd 16 , cc 16 ) timer a9 register (addresses cf 16 , ce 16 ) gate function select bits (note) count source select bits see table 7.2.3. no gate function 0 aaa aaa aaa count starts. aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa setting count start bit to 1. b7 b0 count start register 0 (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa setting interrupt priority level b7 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) (i = 5 to 9) (addresses f5 16 to f9 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. setting port p6 and port p2 direction registers b7 b0 port p6 direction register (address 10 16 ) pin ta0 in pin ta1 in when gate function is selected, clear the bit corresponding to the taj in pin to 0. note: in timers a3, a5 to a8, do not set the above registers. b7 b0 port p2 direction register (address 8 16 ) pin ta4 in pin ta2 in pin ta9 in note: valid only in timer aj (j = 0 to 2, 4, 9). invalid in timer ak (k = 3, 5 to 8); therefore, fix each of these bits to 0. b7 b0 count start register 1 (address 41 16 ) timer a5 count start bit timer a6 count start bit timer a7 count start bit timer a8 count start bit timer a9 count start bit a aa aa a aa a aa aa aa aa a a aa aa a a 0 0 : 0 1 :
timer a 7906 group user s manual rev.2.0 7-14 7.3 timer mode fig. 7.3.3 example of operation in timer mode (without pulse output and gate functions) 7.3.2 operation in timer mode ? when the count start bit is set to 1, the counter starts counting of the count source. ? when a counter underflow occurs, the reload register s contents are reloaded, and counting continues. ? the timer ai interrupt request bit is set to 1 at the underflow in ? . the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. figure 7.3.3 shows an example of operation in the timer mode. stops counting. restarts counting. ffff 16 n 0000 16 time count start bit timer ai interrupt request bit counter contents (hex.) cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. (1 / f i ) ? (n+1) cleared to 0 by software. set to 1 by software. f i : frequency of count source n : reload register s contents
timer a 7906 group user s manual rev.2.0 7-15 7.3 timer mode 7.3.3 select function in timer aj (j = 0 to 2, 4, 9), the gate function or pulse output function can be selected. the following describes the gate and pulse output functions. (1) gate function the gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 56 16 to 58 16 , 5a 16 , da 16 ) to 10 2 or 11 2 . the gate function makes it possible to start or stop counting depending on the taj in pin s input signal. table 7.3.2 lists the count valid levels. figure 7.3.4 shows an example of operation with the gate function selected. when selecting the gate function, set the port p2 and port p6 direction registers bits which correspond to the taj in pins for the input mode. additionally, make sure that the taj in pin s input signal has a pulse width equal to or more than two cycles of the count source. table 7.3.2 count valid levels gate function select bits count valid level (duration while counter counts) b4 b3 1 0 while taj in pin s input signal level is at l level 1 1 while taj in pin s input signal level is at h level note: the counter does not count while the taj in pin s input signal is not at the count valid level. fig. 7.3.4 example of operation with gate function selected ffff 16 n 0000 16 time ? starts counting. counter contents (hex.) ? stops counting. set to 1 by software. count start bit taj in pin s input signal count valid level timer aj interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. ? the counter counts while the count start bit = 1 and the taj in pin s input signal is at the count valid level. ? the counter stops counting while the taj in pin s input signal is not at the count valid level, and the counter value is retained. invalid level n : reload register s contents
timer a 7906 group user s manual rev.2.0 7-16 (2) pulse output function the pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 56 16 to 58 16 , 5a 16 , da 16 ) to 1. when this function is selected, the taj out pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port p2 and port p6 direction registers. the taj out pin outputs a pulse of which polarity is inverted each time a counter underflow occurs. when the count start bit (addresses 40 16 , 41 16 ) is 0 (count stopped), the taj out pin outputs l level. figure 7.3.5 shows an example of operation with the pulse output function selected. 7.3 timer mode fig. 7.3.5 example of operation with pulse output function selected ffff 16 n 0000 16 time count start bit timer aj interrupt request bit counter contents (hex.) cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. pulse output from taj out pin set to 1 by software. cleared to 0 by software. starts counting. restarts counting. n : reload register s contents
timer a 7906 group user? manual rev.2.0 7-17 [precautions for timer mode] [precautions for timer mode] 1. each of timers a3, a5 to a8 is not equipped with the gate function and pulse output function. 2. by reading the timer ai register, the counter value can be read out at arbitrary timing. however, if the timer ai register is read at the reload timing shown in figure 7.3.6, the value ?fff 16 ?is read out. if reading is performed in the period from when a value is set into the timer ai register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 7.3.6 reading timer ai register 210 nn 1 counter value (hex.) 21 0 ffff n 1 read value (hex.) reload time n : reload register s contents
timer a 7906 group user s manual rev.2.0 7-18 item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing taj in pin s function taj out pin s function read from timer aj register write to timer aj register specifications external signal input to the taj in pin the count source s valid edge can be selected from the falling edge and the rising edge by software. countup or countdown can be switched by external signal or software. when a counter overflow or underflow occurs, reload register s con- tents are reloaded, and counting continues. for countdown for countup when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter overflow or underflow occurs. count source input programmable i/o port pin, pulse output pin, or countup/countdown switch signal input pin counter value can be read out. while counting is stopped when a value is written to timer aj register, it is written to both of the reload register and counter. while counting is in progress when a value is written to timer aj register, it is written only to the reload register. (transferred to the counter at the next reload timing.) 7.4 event counter mode timer aj (j = 0 to 2, 4, 9) is equipped with the event counter mode. in this mode, the timer counts an external signal. tables 7.4.1 and 7.4.2 list the specifications of the event counter mode. figure 7.4.1 shows the structures of the timer aj register and timer aj mode register in the event counter mode. each of timers a3, a5 to a8 is not equipped with this mode. table 7.4.1 specifications of event counter mode (when not using two-phase pulse signal processing function) (n + 1) 1 (ffff 16 n + 1) 1 n: timer aj register s set value 7.4 event counter mode
timer a 7906 group user s manual rev.2.0 7-19 item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing function of the following pins: ta2 in , ta2 out ta4 in , ta4 out ta9 in , ta9 out read from timer a2/a4/a9 register write to timer a2/a4/a9 register specifications external signal (two-phase pulse) input to the following pins: ta2 in , ta2 out ta4 in , ta4 out ta9 in , ta9 out countup or countdown can be switched by external signal (two- phase pulse). when a counter overflow or underflow occurs, reload register s con- tents are reloaded, and counting continues. for countdown for countup when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter overflow or underflow occurs. two-phase pulse input counter value can be read out by reading timer a2/a4/a9 register. while counting is stopped when a value is written to timer a2/a4/a9 register, it is written to both of the reload register and counter. while counting is in progress when a value is written to timer a2/a4/a9 register, it is written only to the reload register. (transferred to the counter at the next reload timing.) table 7.4.2 specifications of event counter mode (when using two-phase pulse signal processing function in timers a2, a4, and a9) 7.4 event counter mode (n + 1) 1 1 n: timer a2/a4/a9 register s set value (ffff 16 n + 1)
timer a 7906 group user s manual rev.2.0 7-20 x : it may be either 0 or 1. rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 15 to 0 rw b0 b7 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) b0 b7 (b15) (b8) 0 1 2 3 4 5 6 7 timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits pulse output function select bit count polarity select bit up-down switching factor select bit fix this bit to 0 in event counter mode. these bits are invalid in event counter mode. b7 b6 b5 b4 b3 b2 b1 b0 0 1 : event counter mode b1 b0 01 0 : no pulse output (taj out pin functions as a programmable i/o port pin.) 1 : pulse output (taj out pin functions as a pulse output pin.) xx0 0 : counts at falling edge of external signal 1 : counts at rising edge of external signal 0 : contents of up-down register 1 : input signal to taj out pin bit function at reset r/w bit name bit function at reset r/w undefined any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (ffff 16 n + 1) during countup. when reading, the register indicates the counter value. note: reading from or writing to this register must be performed in a unit of 16 bits. 7.4 event counter mode fig. 7.4.1 structures of timer aj register and timer aj mode register in event counter mode
timer a 7906 group user s manual rev.2.0 7-21 7.4 event counter mode 7.4.1 setting for event counter mode figures 7.4.2 and 7.4.3 show an initial setting example for registers related to the event counter mode. note that when using interrupts, set up to enable the interrupts. for details, refer to ?hapter 6. interrupts. fig. 7.4.2 initial setting example for registers related to event counter mode (1) ? the counter divides the count source frequency by (n + 1) when counting down, or by (ffff 16 n + 1) when counting up. continued to figure 7.4.3 on the next page b7 b0 01 0 selecting event counter mode and each function timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) pulse output function select bit 0: no pulse output 1: pulse output count polarity select bit 0: counts at falling edge of external signal. 1: counts at rising edge of external signal. up-down switching factor select bit 0: contents of up-down register 1: input signal to taj out pin selection of event counter mode setting divide ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) x: it may be either 0 or 1. ? ? b7 b0 setting up down register up down register 0 (address 44 16 ) timer a1 up down bit timer a0 up down bit timer a2 up down bit timer a4 up down bit timer a2 two phase pulse signal processing select bit timer a4 two phase pulse signal processing select bit set to the corresponding up down bit when the contents of the up-down register are selected as the up-down switching factor. 0: countdown 1: countup 0: two phase pulse signal processing function disabled 1: two phase pulse signal processing function enabled set the corresponding bit to 1 when the two phase pulse signal processing function is selected for timers a2 and a4. b7 b0 up down register 1 (address c4 16 ) timer a9 up down bit timer a9 two phase pulse signal processing select bit set to the corresponding up down bit when the contents of the up-down register are selected as the up-down switching factor. 0: countdown 1: countup 0: two phase pulse signal processing function disabled 1: two phase pulse signal processing function enabled set the corresponding bit to 1 when the two phase pulse signal processing function is selected for timer a9. 00 00 0000
timer a 7906 group user s manual rev.2.0 7-22 7.4 event counter mode fig. 7.4.3 initial setting example for registers relevant to event counter mode (2) aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aa aa b7 aa aa b0 aaaaaa aaaaaaa setting the count start bit to 1 aaaaa aaaaa count start register 0 (address 40 16 ) aaaa timer a0 count start bit aaaa aaaa timer a1 count start bit aaaa timer a2 count start bit aaaa timer a4 count start bit aa aa aaaa aaaa aaaa aaaa aaa aaa count starts. continued from preceding figure 7.4.2 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa setting port p6 and port p2 direction registers b7 b0 port p6 direction register (address 10 16 ) pin ta0 out pin ta0 in aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaa aaaaaaa setting interrupt priority level aa b7 aa b0 timer aj interrupt control register (j = 0 to 2, 4, 9) (addresses 75 16 to 77 16 , 79 16 , f9 16 ) aa aa a a aa aa a a aa aa aa aa a a aaa aaa aaa aa aa aa interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. b7 b0 port p2 direction register (address 8 16 ) clear the bit corresponding to the taj in pin to 0. when selecting the taj out pin s input signal as up-down switching factor, clear the bit corresponding to the taj out pin to 0. when selecting the two phase pulse signal processing function, clear the bits corresponding to the ta2 out , ta4 out , and ta9 out pins to 0. pin ta4 out pin ta1 out pin ta1 in pin ta4 in pin ta2 out pin ta2 in pin ta9 out pin ta9 in aa b7 aa b0 aaaaa aaaaa count start register 1 (address 41 16 ) aaaa timer a9 count start bit aaaa aaaa a a aa aa a a aa aa aa aa a a a aa a aa aa
timer a 7906 group user s manual rev.2.0 7-23 7.4.2 operation in event counter mode ? when the count start bit is set to 1, the counter starts counting of the count source s valid edge. ? when a counter underflow or overflow occurs, the reload register s contents are reloaded, and counting continues. ? the timer aj interrupt request bit is set to 1 at the underflow or overflow in ? . the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. figure 7.4.4 shows an example of operation in the event counter mode. 7.4 event counter mode fig. 7.4.4 example of operation in event counter mode (without pulse output and two-phase pulse signal processing functions) timer aj interrupt request bit ffff 16 n 0000 16 time count start bit counter contents (hex.) cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. up-down bit note: the above applies when the up-down bit s contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = 0 ). set to 1 by software. n : reload register s contents
timer a 7906 group user s manual rev.2.0 7-24 7.4 event counter mode 7.4.3 switching between countup and countdown figure 7.4.5 shows structures of the up-down registers 0 and 1. the up-down register or the input signal from the taj out pin is used to switch countup from and to countdown. this switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 56 16 to 58 16 , 5a 16 , da 16 ) is 0, and by the input signal from the taj out pin when the up- down switching factor select bit is 1. when the switching between countup and countdown is set while counting is in progress, this switching is actually performed when the count source s next valid edge is input. (1) switching by up-down bit countdown is performed when the up-down bit is 0, and countup is performed when the up-down bit is 1. figure 7.4.5 shows the structures of the up-down registers 0 and 1. (2) switching by taj out pin s input signal countdown is performed when the taj out pin s input signal is at l level, and countup is performed when the taj out pin s input signal is at h level. when using the taj out pin s input signal to switch countup from and to countdown, set the port p2 and port p6 direction registers bits which correspond to the taj out pin for the input mode.
timer a 7906 group user s manual rev.2.0 7-25 fig. 7.4.5 structures of up-down registers 0 and 1 b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 up-down register 0 (address 44 16 ) timer a0 up-down bit timer a1 up-down bit timer a2 up-down bit fix this bit to 0. timer a4 up-down bit timer a2 two-phase pulse signal processing select bit fix this bit to 0. timer a4 two-phase pulse signal processing select bit 0 : countdown 1 : countup this function is valid when the contents of the up- down register is selected as the up-down switching factor. 0 : countdown 1 : countup this function is valid when the contents of the up- down register is selected as the up-down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, clear the bit to 0. the value is 0 at reading. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, clear the bit to 0. the value is 0 at reading. 0 0 0 0 0 0 0 0 rw rw rw rw rw wo (note) wo (note) wo (note) note: use the movm (movmb) or sta(stab, stad) instruction for writing to bits 5 to 7. bit name bit function at reset r/w 00 b7 b6 b5 b4 b3 b2 b1 b0 3 to 0 4 6, 5 7 up-down register 1 (address c4 16 ) fix these bits to 0000. timer a9 up-down bit fix these bits to 00. timer a9 two-phase pulse signal processing select bit 0 : countdown 1 : countup this function is valid when the contents of the up- down register is selected as the up-down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, clear the bit to 0. the value is 0 at reading. 0 0 0 0 rw rw wo (note) wo (note) note: use the movm(movmb) or sta(stab, stad) instruction for writing to bits 5 to 7. bit name bit function at reset r/w 00 000 0 7.4 event counter mode
timer a 7906 group user s manual rev.2.0 7-26 7.4 event counter mode 7.4.4 selectable functions the following describes the selectable pulse output, and two-phase pulse signal processing functions. (1) pulse output function the pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 56 16 to 58 16 , 5a 16 , da 16 ) to 1. when this function is selected, the taj out pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port p2 and port p6 direction registers. the taj out pin outputs a pulse of which polarity is inverted each time a counter underflow or overflow occurs. (refer to figure 7.3.5). when the count start bit (addresses 40 16 , 41 16 ) is 0 (count stopped), the taj out pin outputs l level. (2) two-phase pulse signal processing function (timers a2, a4, a9) for timers a2, a4, a9, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing select bits (bits 5 and 7 at address 44 16 , bit 7 at address c4 16 ) to 1. (see figure 7.4.5.) figure 7.4.6 shows the timer a2/a4/a9 mode registers when the two-phase pulse signal processing function is selected. for timers with two-phase pulse signal processing function selected, the timer counts two kinds of pulses of which phases differ by 90 degrees. there are two types of the two-phase pulse signal processing: normal processing and quadruple processing. in timer a2, normal processing is performed; in timers a4 and a9, quadruple processing is performed. for the port p2 and p6 direction registers bits corresponding to the pins used for two-phase pulse input, be sure to set these bits for the input mode. fig. 7.4.6 timer a2/a4/a9 mode registers when two-phase pulse signal processing function is selected 1 00001 timer a2 mode register (address 58 16 ) timer a4 mode register (address 5a 16 ) timer a9 mode register (address 5d 16 ) b7 b6 b5 b4 b3 b2 b1 b0 ? : it may be either 0 or 1. ??
timer a 7906 group user s manual rev.2.0 7-27 input signal to tam out pin countup is performed at the rising edges input to the ta2 in pin when the ta2 in and ta2 out have the relationship that the ta2 in pin s input signal goes from l to h while the ta2 out pin s input signal is at h level. countdown is performed at the falling edges input to the ta2 in pin when the ta2 in and ta2 out have the relationship that the ta2 in pin s input signal goes from h to l while the ta2 out pin s input signal is h. (see figure 7.4.7.) countup is performed at all rising and fall- ing edges input to the tam out and tam in pins when the tam in and tam out have the relationship that the tam in pin s input sig- nal level goes from l to h while the tam out pin s input signal is at h level. countdown is performed at all rising and falling edges input to the tam out and tam in pins when the tam in and tam out have the relationship that the tam in pin s input sig- nal level goes from h to l while the tam out pin s input signal is at h level. (see figure 7.4.8.) table 7.4.3 lists the input signals on the tam out and tam in pins when the quadruple processing is selected. fig. 7.4.7 normal processing table 7.4.3 tam out and tam in pin s input signals when quadruple processing is selected h level l level rising edge falling edge h level l level rising edge falling edge rising edge falling edge l level h level falling edge rising edge h level l level countup countdown fig. 7.4.8 quadruple processing input signal to tam in pin 7.4 event counter mode tam out tam in h h l l +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 counted up at all edges. 1 1 1 1 1 1 1 1 1 1 counted down at all edges. counted up at all edges. counted down at all edges. ta2 out ta2 in h h l +1 +1 +1 1 1 1 l countup countup countup countdown countdown countdown
timer a 7906 group user s manual rev.2.0 7-28 [precautions for event counter mode] 1. each of timers a3, a5 to a8 is not equipped with the event counter mode. 2. while counting is in progress, by reading the timer aj (j = 0 to 2, 4, 9) register, the counter value can be read out at any timing. however, if the timer aj register is read at the reload timing shown in figure 7.4.9, the value ffff 16 (at an underflow) or 0000 16 (at the overflow) is read out. if reading is performed in the period from when a value is set into the timer aj register with the counter stopped until the counter starts counting, the set value is correctly read out. [precautions for event counter mode] fig. 7.4.9 reading timer aj register 3. the taj out pin is used for all functions listed below. accordingly, only one of these functions can be selected for each timer. switching between countup and countdown by taj out pin s input signal pulse output function two-phase pulse signal processing function (timers a2, a4, a9) 210 n n 1 counter value (hex.) 210 ffff n 1 read value (hex.) reload time n : reload register s contents (1) for countdown fffd fffe ffff n n + 1 fffd fffe ffff 0000 n + 1 (2) for countup counter value (hex.) read value (hex.) reload time n : reload register s contents
timer a 7906 group user s manual rev.2.0 7-29 item count source f i count operation output pulse width ( h ) count start condition count stop condition interrupt request occurrence timing taj in pin s function taj out pin s function read from timer aj register write to timer aj register specifications f 1 , f 2 , f 16 , f 64 , f 512 , or f 4096 countdown when the counter value becomes 0000 16 , reload register s con- tents are reloaded, and counting stops. if a trigger occurs during counting, reload register s contents are reloaded, and counting continues. when a trigger occurs. (note) internal or external trigger can be selected by software. when the counter value becomes 0000 16 when the count start bit is cleared to 0 when counting stops. programmable i/o port pin or trigger input pin one-shot pulse output an undefined value is read out. while counting is stopped when a value is written to timer aj register, it is written to both of the reload register and counter. while counting is in progress when a value is written to timer aj register, it is written only to the reload register. (transferred to counter at the next reload timing.) 7.5 one-shot pulse mode timer aj (j = 0 to 2, 4, 9) is equipped with the one-shot pulse mode. in this mode, the timer outputs a pulse which has an arbitrary width once. when a trigger occurs, the timer outputs h level from the taj out pin for an arbitrary time. table 7.5.1 lists the specifications of the one-shot pulse mode. figure 7.5.1 shows the structures of the timer aj register and timer aj mode register in the one-shot pulse mode. each of timers a3, a5 to a8 is not equipped with this mode. table 7.5.1 specifications of one-shot pulse mode 7.5 one-shot pulse mode n f i [s] n : timer aj register s set value note: the trigger is generated with the count start bit = 1.
timer a 7906 group user s manual rev.2.0 7-30 rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits fix this bit to 1 in one-shot pulse mode. trigger select bits fix this bit to 0 in one-shot pulse mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 1 0 : one-shot pulse mode b1 b0 10 0 0 0 : writing 1 to one-shot start bit 0 1 : (taj in pin functions as a programmable i/o port pin.) 1 0 : falling edge of taj in pin s input signal 1 1 : rising edge of taj in pin s input signal b4 b3 1 0 0 0 0 0 0 0 0 see table 7.2.3. undefined 15 to 0 any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the h level width of the one-shot pulse which is output from the taj out pin is expressed as follows : wo b0 b7 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) b0 b7 (b15) (b8) f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. n f i . bit function at reset r/w bit name bit function at reset r/w fig. 7.5.1 structures of timer aj register and timer aj mode register in one-shot pulse mode 7.5 one-shot pulse mode
timer a 7906 group user s manual rev.2.0 7-31 7.5.1 setting for one-shot pulse mode figures 7.5.2 and 7.5.3 show an initial setting example for registers related to the one-shot pulse mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 6. interrupts. 7.5 one-shot pulse mode fig. 7.5.2 initial setting example for registers related to one-shot pulse mode (1) continued to figure 7.5.3 on the next page aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa setting interrupt priority level b7 b0 timer aj interrupt control register (j = 0 to 2, 4, 9) (addresses 75 16 to 77 16 , 79 16 , f9 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa b7 b0 10 0 selecting one-shot pulse mode and each function timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) 1 trigger select bits 0 0 : 0 1 : 1 0 : falling of taj in pin s input signal: external trigger 1 1 : rising of taj in pin s input signal: external trigger b4 b3 count source select bits see table 7.2.3. selection of one-shot pulse mode aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa setting h level width of one-shot pulse b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) h level width = f i = frequency of count source however, if n = 0000 16 , the counter does not operate and the taj out pin outputs l level. at this time, no timer aj interrupt request occurs. writing 1 to one-shot start bit: internal trigger f i note . n
timer a 7906 group user s manual rev.2.0 7-32 7.5 one-shot pulse mode fig. 7.5.3 initial setting example for registers related to one-shot pulse mode (2) aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaa aaa aaa aaa count starts. trigger generated b7 b0 aaaaaa aaaaaa port p6 direction register (address 10 16 ) aaaaaaaaaa aaaaaaaaaa setting port p6 and port p2 direction registers aaa aaa pin ta0 in aaa pin ta1 in aaaaaaa clear the corresponding bit to 0. aaaaaa aaaaaa trigger input to taj in pin when internal trigger is selected when external trigger is selected continued from preceding figure 7.5.2 aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaa aaaaaa port p2 direction register (address 8 16 ) aaa aaa pin ta4 in b7 b0 aa aa aaa aaa pin ta2 in aaa pin ta9 in aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaa setting count start bit to 1 b7 b0 aaaaa timer a0 count start bit aaaaa aaaaa timer a1 count start bit aaaaa aaaaa timer a2 count start bit aaaaa timer a4 count start bit aa aa aaaa aaaa aaaa aaaa aaa aaa aaa aa aa aa aaaaa aaaaa count start register 0 (address 40 16 ) b7 b0 aaaaa timer a9 count start bit aaaa aaaa aaaaa aaaaa count start register 1 (address 41 16 ) aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aa aa b7 aa aa b0 aaaa aaaa aaaa aaaa one-shot start register 0 (address 42 16 ) aaaaaaa setting one-shot start bit to 1 timer a0 one-shot start bit aaa aaa aaa aa aa aa a a aaa aa a aa aa a aa aa aa b7 aa aa b0 aaaa aaaa one-shot start register 1 (address 43 16 ) timer a9 one-shot start bit aaa aa a aa aa a aa aaaaaaa aaaaaaa setting count start bit to 1 b7 b0 aaaaa aaaaa timer a0 count start bit aaaaa timer a1 count start bit aaaaa timer a2 count start bit aaaaa aaaaa timer a4 count start bit a aaa aaa aaa aa aa aa aa aa aaaaa aaaaa count start register 0 (address 40 16 ) b7 b0 aaaa aaaa timer a9 count start bit aaa aaa aaaaa aaaaa count start register 1 (address 41 16 ) aa aa a a aa aa a a aa aa aa aa aa aa aa aa a a aa aa a a a a aa aa a a aa aa aa aa 00 0000 0 timer a1 one-shot start bit timer a2 one-shot start bit timer a4 one-shot start bit
timer a 7906 group user? manual rev.2.0 7-33 7.5.2 trigger the counter is enabled for counting when the count start bit (addresses 40 16 , 41 16 ) has been set to ?.? the counter starts counting when a trigger is generated after counting has been enabled. an internal or external trigger can be selected as that trigger. an internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 58 16 , 5a 16 , da 16 ) are ?0 2 ?or ?1 2 ? an external trigger is selected when the bits are ?0 2 ?or ?1 2 . if a trigger is generated during counting, the reload register? contents are reloaded and the counter continues counting. if a trigger generated during counting, make sure that a certain time which is equivalent to one cycle of the timer? count source or more has passed between the previously trigger occurrence and a new trigger occurrence. (1) when selecting internal trigger a trigger is generated when writing ??to the one-shot start bit (addresses 42 16 , 43 16 ). figure 7.5.4 shows the structures of the one-shot start registers 0 and 1. (2) when selecting external trigger a trigger is generated at the falling edge of the taj in pin? input signal when bit 3 at addresses 56 16 to 58 16 , 5a 16 , da 16 is ?,?or at its rising edge when bit 3 is ?. when using an external trigger, set the port p2 and port p6 direction registers?bits which correspond to the taj in pins for the input mode. 7.5 one-shot pulse mode
timer a 7906 group user? manual rev.2.0 7-34 fig. 7.5.4 structures of one-shot start registers 0 and 1 7.5 one-shot pulse mode 0 1 2 3 4 6, 5 7 wo wo wo wo wo rw 0 0 0 0 0 undefined 0 one-shot start register 0 (address 42 16 ) b7 b6 b5 b4 b3 b2 b1 b0 1 : start outputting one-shot pulse. (valid when an internal trigger is selected.) the value is ??at reading. 0 timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit fix this bit to ?. timer a4 one-shot start bit nothing is assigned. fix this bit to ?. bit name bit function at reset r/w 1 : start outputting one-shot pulse. (valid when an internal trigger is selected.) the value is ??at reading. 3 to 0 4 6, 5 7 wo wo rw 0 0 undefined 0 one-shot start register 1 (address 43 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 fix these bits to ?000. timer a9 one-shot start bit nothing is assigned. fix this bit to ?. bit name bit function at reset r/w 1 : start outputting one-shot pulse. (valid when an internal trigger is selected.) the value is ??at reading. 0 0000
timer a 7906 group user? manual rev.2.0 7-35 7.5 one-shot pulse mode 7.5.3 operation in one-shot pulse mode ? when the one-shot pulse mode is selected with the operating mode select bits, the taj out pin outputs ??level. ? when the count start bit is set to ?,?the counter is enabled for counting. after that, counting starts when a trigger is generated. ? when the counter starts counting, the taj out pin outputs ??level. (when a value of ?000 16 ?is set to the timer aj register, the counter stops operating, the output level at pin taj out remains ?,?and no timer aj interrupt request does not occur.) ? when the counter value becomes ?000 16 ,?the output from the taj out pin becomes ??level. additionally, the reload register? contents are reloaded and the counter stops counting there. ? simultaneously with ? , the timer aj interrupt request bit is set to ?. this interrupt request bit remains set to ??until the interrupt request is accepted or until the interrupt request bit is cleared to ??by software. figure 7.5.5 shows an example of operation in the one-shot pulse mode. when a trigger is generated after ? above, the counter and taj out pin perform the same operations beginning from ? again. furthermore, if a trigger is generated during counting, the counter performs countdown once after this new trigger is generated, and then, it continues counting with the reload register? contents reloaded. if generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer? count source or more has passed between the previously trigger occurrence and a new trigger occurrence. the one-shot pulse output from the taj out pin can be disabled by clearing the timer aj mode register? bit 2 to ?.?accordingly, timer aj can also be used as an internal one-shot timer that does not perform the pulse output. in this case, the taj out pin functions as a programmable i/o port pin.
timer a 7906 group user? manual rev.2.0 7-36 7.5 one-shot pulse mode fig. 7.5.5 example of operation in one-shot pulse mode (selecting external trigger) stops counting. starts counting. ffff 16 n 0001 16 time ? count start bit timer aj interrupt request bit counter contents (hex.) n = reload register s contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. taj in pin input signal one-shot pulse output from taj out pin ? trigger during counting (1 / f i ) ? (n) note: the above applies when an external trigger (rising edge of taj in pin s input signal) is selected. (1 / f i ) ? (n + 1) ? when the count start bit = 0 (counting stopped), the taj out pin outputs l level. ? when a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generate d. f i : frequency of count source stops counting. reloaded reloaded n : reload register s contents
timer a 7906 group user s manual rev.2.0 7-37 [precautions for one-shot pulse mode] [precautions for one-shot pulse mode] 1. each of timers a3, a5 to a8 is not equipped with the one-shot pulse mode. 2. if the count start bit is cleared to 0 during counting, the counter becomes as follows: the counter stops counting, and the reload register s contents are reloaded into the counter. the taj out pin s output level becomes l. the timer aj interrupt request bit is set to 1. 3. a one-shot pulse is output synchronously with an internally generated count source. accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum, in a period from when a trigger is input to the taj in pin until a one-shot pulse is output. fig. 7.5.6 output delay in one-shot pulse output 4. when the timer s operating mode has been set by one of the following procedures, the timer aj interrupt request bit will be set to 1. when the one-shot pulse mode is selected after reset when the operating mode is switched from the timer mode to the one-shot pulse mode when the operating mode is switched from the event counter mode to the one-shot pulse mode accordingly, when using a timer aj interrupt (interrupt request bit), be sure to clear the timer aj interrupt request bit to 0 after the above setting. note: the above applies when an external trigger (falling edge of taj in pin s input signal) is selected. taj in pin s input signal count source trigger input starts outputting of one-shot pulse one-shot pulse output from taj out pin
timer a 7906 group user s manual rev.2.0 7-38 7.6 pulse width modulation (pwm) mode 7.6 pulse width modulation (pwm) mode timer aj (j = 0 to 2, 4, 9) is equipped with the pulse width modulation (pwm) mode. in this mode, the timer continuously outputs pulses which have an arbitrary width. table 7.6.1 lists the specifications of the pwm mode. figure 7.6.1 shows the structures of the timer aj register and timer aj mode register in the pwm mode. each of timers a3, a5 to a8 is not equipped with this mode. table 7.6.1 specifications of pwm mode item count source f i count operation pwm period/ h level width count start condition count stop condition interrupt request occurrence timing taj in pin s function taj out pin s function read from timer aj register write to timer aj register specifications f 1 , f 2 , f 16 , f 64 , f 512 , or f 4096 countdown (operating as an 8-bit or 16-bit pulse width modulator) reload register s contents are reloaded at rising edge of pwm pulse, and counting continues. a trigger generated during counting does not affect the counting. <16-bit pulse width modulator> <8-bit pulse width modulator> when a trigger is generated. (note) internal or external trigger can be selected by software. when the count start bit is cleared to 0. at falling edge of pwm pulse programmable i/o port pin or trigger input pin pwm pulse output an undefined value is read out. while counting is stopped when a value is written to the timer aj register, it is written to both of the reload register and counter. while counting is in progress when a value is written to the timer aj register, it is written only to the reload register. (transferred to the counter at the next reload time.) period = (2 16 1) f i [s] h level width = [s] period = (m + 1)(2 8 1) f i h level width = [s] n(m + 1) f i n : timer aj register s set value [s] m : timer aj register s low-order 8 bits set value n : timer aj register s high-order 8 bits set value note: the trigger is generated with the count start bit = 1. n f i
timer a 7906 group user s manual rev.2.0 7-39 7.6 pulse width modulation (pwm) mode rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 timer aj mode register (i = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits fix this bit to 1 in pwm mode. trigger select bits 16/8-bit pwm mode select bit count source select bits b7 b6 b5 b4 b3 b2 b1 b0 1 1 : pwm mode b1 b0 11 0 0 : writing 1 to count start bit 0 1 : (taj in pin functions as a programmable i/o port pin.) 1 0 : falling edge of taj in pin s input signal 1 1 : rising edge of taj in pin s input signal b4 b3 1 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 0 0 0 0 0 0 0 see table 7.2.3. timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined 15 to 0 any value in the range from 0000 16 to fffe 16 can be set. assuming that the set value = n, the h level width of the pwm pulse which is output from the taj out pin is expressed as follows : (pwm pulse period = ) wo b0 b7 b0 b7 (b15) (b8) f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. n f i 2 16 1 f i timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined undefined 7 to 0 15 to 8 any value in the range from 00 16 to ff 16 can be set. assuming that the set value = m, the period of the pwm pulse which is output from the taj out pin is expressed as follows: wo wo b0 b7 b0 b7 (b15) (b8) (m + 1) (2 8 1) f i any value in the range from 00 16 to ff 16 can be set. assuming that the set value = n, the h level width of the pwm pulse which is output from the taj out pin is expressed as follows: n(m + 1) f i f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. bit function at reset r/w bit name bit function at reset r/w bit function at reset r/w fig. 7.6.1 structures of timer aj register and timer aj mode register in pwm mode
timer a 7906 group user s manual rev.2.0 7-40 7.6 pulse width modulation (pwm) mode 7.6.1 setting for pwm mode figures 7.6.2 and 7.6.3 show an initial setting example for registers relevant to the pwm mode. note that when using interrupts, set up to enable the interrupts. for details, refer to ?hapter 6. interrupts. fig. 7.6.2 initial setting example for registers related to pwm mode (1) note . when operating as 8-bit pulse width modulator (m+1) (2 1) f i n(m+1) f i however, if n = 00 16 , the pulse width modulator does not operate and the taj out pin outputs l level. at this time, no timer aj interrupt request occurs. aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa b7 b0 count source select bits see table 7.2.3. 11 selecting pwm mode and each function timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) 1 16/8-bit pwm mode select bit 0 : operates as 16-bit pulse width modulator 1 : operates as 8-bit pulse width modulator continued to figure 7.6.3 on the next page trigger select bits 0 0 : 0 1 : 1 0 : falling edge of taj in pin s input signal: external trigger 1 1 : rising edge of taj in pin s input signal: external trigger b3 b4 selection of pwm mode aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa setting pwm pulse s period and h level width b7 b0 can be set to 0000 16 to fffe 16 (n) (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) note. when operating as 16-bit pulse width modulator 2 1 f i n f i however, if n = 0000 16 , the pulse width modulator does not operate and the taj out pin outputs l level. at this time, no timer aj interrupt request occurs. when operating as 16-bit pulse width modulator b7 b0 can be set to 00 16 to ff 16 (m) (b15) (b8) b7 b0 when operating as 8-bit pulse width modulator can be set to 00 16 to fe 16 (n) 16 8 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) writing 1 to count start bit: internal trigger period = h level width = period = h level width = (f i : frequency of count source) (f i : frequency of count source)
timer a 7906 group user s manual rev.2.0 7-41 7.6 pulse width modulation (pwm) mode fig. 7.6.3 initial setting example for registers related to pwm mode (2) aaa aaa aaa count starts. when external trigger is selected when internal trigger is selected continued from preceding figure 7.6.2 trigger generated aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa b7 b0 aaaaa port p6 direction register (address 10 16 ) aaaaaaaaa setting port p6 and port p2 direction registers aaaaaaa clear the corresponding bit to 0. aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa setting interrupt priority level b7 b0 timer aj interrupt control register (j = 0 to 2, 4, 9) (addresses 75 16 to 77 16 , 79 16 , f9 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. aaaaa aaaaa trigger input to taj in pin aaa pin ta0 in aaa aaa pin ta1 in aa pin ta4 in b7 b0 aa aa aaaaa aaaaa port p2 direction register (address 8 16 ) aaa pin ta2 in aa aa pin ta9 in aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaa setting count start bit to 1 b7 b0 aaaaa count start register 0 (address 40 16 ) aaaaa timer a0 count start bit aaaaa aaaaa timer a1 count start bit aaaaa timer a2 count start bit aaaaa timer a4 count start bit a a aaa aaa aaa aaa aa aa aa a a a b7 b0 aaaaa aaaaa count start register 1 (address 41 16 ) aaaaa timer a9 count start bit aaa aaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaa setting count start bit to 1 b7 b0 aaaaa aaaaa count start register 0 (address 40 16 ) aaaa timer a0 count start bit aaaa timer a1 count start bit aaaa aaaa timer a2 count start bit aaaa timer a4 count start bit aa aa aaaa aaaa aaaa aaaa aaa aaa aaa aa aa aa b7 b0 aaaaa aaaaa count start register 1 (address 41 16 ) aaaaa timer a9 count start bit aaaa aaaa aa a a aa
timer a 7906 group user s manual rev.2.0 7-42 7.6 pulse width modulation (pwm) mode 7.6.2 trigger when a trigger is generated, the taj out pin starts to output pwm pulses. an internal or an external trigger can be selected as that trigger. an internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 58 16 , 5a 16 , da 16 ) are 00 2 or 01 2 ; an external trigger is selected when these bits are 10 2 or 11 2 . a trigger generated during pwm pulse output is invalid, and it does not affect the pulse output operation. (1) when selecting internal trigger a trigger is generated when 1 is written to the count start bit (addresses 40 16 , 41 16 ). (2) when selecting external trigger a trigger is generated at the falling edge of the taj in pin s input signal when bit 3 at addresses 56 16 to 58 16 , 5a 16 , da 16 is 0, or at its rising edge when bit 3 is 1. however, the trigger input is acceptable only when the count start bit is 1. when using an external trigger, set the port p2 and port p6 direction registers bits which correspond to the taj in pins for the input mode.
timer a 7906 group user s manual rev.2.0 7-43 7.6 pulse width modulation (pwm) mode 7.6.3 operation in pwm mode ? when the pwm mode is selected with the operating mode select bits, the taj out pin outputs l level. ? when a trigger is generated, the counter (pulse width modulator) starts counting and the taj out pin outputs a pwm pulse ( notes 1 and 2 ). ? the timer aj interrupt request bit is set to 1 each time the pwm pulse level goes from h to l. the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. ? each time a pwm pulse has been output for one period, the reload register s contents are reloaded and the counter continues counting. the following explains operations of the pulse width modulator. (1) 16-bit pulse width modulator when the 16/8-bit pwm mode select bit is cleared to 0, the counter operates as a 16-bit pulse width modulator. figures 7.6.4 and 7.6.5 show operation examples of the 16-bit pulse width modulator. (2) 8-bit pulse width modulator when the 16/8-bit pwm mode select bit is set to 1, the counter is divided into 8-bit halves. then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. figures 7.6.6 and 7.6.7 show operation examples of the 8-bit pulse width modulator. notes 1: if a value 0000 16 is set into the timer aj register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the taj out pin remains l level. the timer aj interrupt request does not occur. similarly, if a value 00 16 is set into the high-order 8 bits of the timer aj register when the counter operates as an 8-bit pulse width modulator, the same is performed. 2: when the counter operates as an 8-bit pulse width modulator, after a trigger is generated, the taj out pin outputs l level for a period of (1 / f i ) ? (m + 1) ? (n + 1). after that, the pwm pulse output will start.
timer a 7906 group user s manual rev.2.0 7-44 7.6 pulse width modulation (pwm) mode fig. 7.6.4 operation example of 16-bit pulse width modulator fig. 7.6.5 operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) (1 / f i ) ? (2 16 1) (1 / f i ) ? (n) count source taj in pin s input signal pwm pulse output from taj out pin note: the above applies when n = 0003 16 and an external trigger (rising edge of taj in pin s input signal) is selected. trigger is not generated by this signal. timer aj interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. f i : frequency of count source n: reload register ? when an arbitrary value is set to the timer aj register after setting 0000 16 to it, the timing when the pwm pulse goes h depends on the timing when the new value is set. note: the above applies when an external trigger (rising edge of taj in pin s input signal) is selected. fffe 16 n 0001 16 taj in pin s input signal counter contents (hex.) (1 / f i ) ? (2 16 1) (2 16 1) n (1 / f i ) ? (2 16 1) pwm pulse output from taj out pin 0000 16 is set to timer aj register. 2000 16 is set to timer aj register. 2000 16 fffe 16 is set to timer aj register. n = reload register s contents f i : frequency of count source restarts counting. stops counting. time (1 / f i ) ? (2 1) 16 ? n: reload register s contents
timer a 7906 group user s manual rev.2.0 7-45 7.6 pulse width modulation (pwm) mode fig. 7.6.6 operation example of 8-bit pulse width modulator ? count source taj in pin s input signal (1 / f i ) ? (m + 1) ? (2 8 1) pwm pulse output from taj out pin note: the above applies when n = 02 16 , m = 02 16 , and an external trigger (falling edge of taj in pin s input signal) is selected. timer aj interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. f i : frequency of count source n: reload register s high-order 8 bits m: reload register s low-order 8 bits ? the 8-bit prescaler counts the count source. ? the 8-bit pulse width modulator counts the 8-bit prescaler s underflow signal. ? 8-bit prescaler s underflow signal (1 / f i ) ? (m + 1) ? (n) (1 / f i ) ? (m + 1)
timer a 7906 group user s manual rev.2.0 7-46 7.6 pulse width modulation (pwm) mode fig. 7.6.7 operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) (1 / f i ) ? (m+1) ? (2 8 1) pwm pulse output from taj out pin ? count source taj in pin s input signal (1 / f i ) ? (m+1) ? (2 8 1) (1 / f i ) ? (m + 1) ? (2 8 1) 00 16 prescaler's contents (hex.) 02 16 time stops counting. 01 16 counter s contents (hex.) 04 16 0a 16 time ? when an arbitrary value is set to the timer aj register after setting 00 16 to it, the timing when the pwm pulse level goes h depends on the timing when the new value is set. 0002 16 is set to timer aj register. 0a02 16 is set to timer aj register. 0402 16 is set to timer aj register. restarts counting. note: the above applies when an external trigger (falling edge of taj in pin s input signal) is selected. f i : frequency of count source m: reload register s low-order 8 bits
timer a 7906 group user s manual rev.2.0 7-47 [precautions for pulse width modulation (pwm) mode] 1. each of timers a3, a5 to a8 is not equipped with the pulse width modulation (pwm) mode. 2. if the count start bit is cleared to 0 during pwm pulse output, the counter stops counting. if the taj out pin outputs h level at that time, the output level will become l and the timer aj interrupt request bit will be set to 1. when the taj out pin outputs l level at that time, the output level will not change and no timer aj interrupt request will occur. 3. when the timer s operating mode is set by one of the following procedures, the timer aj interrupt request bit is set to 1. when the pwm mode is selected after reset when the operating mode is switched from the timer mode to the pwm mode when the operating mode is switched from the event counter mode to the pwm mode accordingly, when using a timer aj interrupt (interrupt request bit), be sure to clear the timer aj interrupt request bit to 0 after the above setting. [precautions for pulse width modulation (pwm) mode]
timer a 7906 group user s manual rev.2.0 7-48 [precautions for pulse width modulation (pwm) mode] memorandum
chapter 8 timer b 8.1 overview 8.2 block description 8.3 timer mode [precautions for timer mode] 8.4 event counter mode [precautions for event counter mode] 8.5 pulse period/pulse width measurement mode [precautions for pulse period/pulse width measurement mode]
7906 group user? manual rev.2.0 8-2 timer b 8.1 overview, 8.2 block description 8.1 overview timer b consists of three counters (timers b0 to b2) each equipped with a 16-bit reload function. timers b0 to b2 have identical functions and operate independently of one other. timer bi (i = 0 to 2) has three operating modes listed below. (1) timer mode the timer counts an internally generated count source. (2) event counter mode the timer counts an external signal. (3) pulse period/pulse width measurement mode the timer measures an external signal? pulse period or pulse width. in this mode, the following count types are available: ?count clear type ?free-run type 8.2 block description figure 8.2.1 shows the block diagram of timer b. explanation of registers relevant to timer b is described below. fig. 8.2.1 block diagram of timer b f 2 f 16 f 64 f 512 count source select bits timer pulse period measurement/pulse width measuremen t event counter mode count start register counter reset circuit data bus (odd) data bus (even) (low-order 8 bits) (high-order 8 bits) timer bi reload register (16) timer bi interrupt request bit tbi in timer bi overflow flag (valid in the pulse period/pulse width measurement mode.) timer bi counter (16) polarity selection and edge pulse generator timer b2 clock source select bit (note) timer b2 clock source select bit : bit 6 at address 63 16 note: only for timer b2, a clock source in the event counter mode can be selected. fx 32
7906 group user s manual rev.2.0 8-3 timer b 8.2.1 counter and reload register (timer bi register) each of timer bi counter and reload register consists of 16 bits and has the following functions. (1) functions in timer mode and event counter mode countdown in the counter is performed each time the count source is input. the reload register is used to store the initial value of the counter. when a counter underflow occurs, the reload register s contents are reloaded into the counter. a value is set to the counter and reload register by writing the value to the timer bi register. table 8.2.1 lists the memory assignment of the timer bi register. the value written into the timer bi register while counting is not in progress is set to the counter and reload register. the value written into the timer bi register while counting is in progress is set only to the reload register. in this case, the reload register s updated contents are transferred to the counter at the next underflow. the counter value is read out by reading out the timer bi register. note: when reading from or writing to the timer bi register, perform it in a unit of 16 bits. for more information about the value obtained by reading the timer bi register, refer to sections ?precautions for timer mode] and ?precautions for event counter mode]. (2) functions in pulse period/pulse width measurement mode countup in the counter is performed each time the count source is input. the reload register is used to retain the pulse period or pulse width measurement result. when a valid edge is input to the tb iin pin, the counter value is transferred to the reload register. in this mode, the value obtained by reading the timer bi register is the reload register s contents, so that the measurement result is obtained. by using the count-type select bit (bit 4 at addresses 5b 16 to 5d 16 ), the count type can be selected from the counter clear type and free-run type. the operation of the counter after the counter value is transferred to the reload register is as follows; in the case of the counter clear type, the counter value becomes 0000 16 ; and counting continues. in the case of the free-run type, the counter value does not become 0000 16 ; and counting continues with this counter value kept. note: when reading from the timer bi register, perform it in a unit of 16 bits. 8.2 block description timer bi register timer b0 register timer b1 register timer b2 register low-order byte address 50 16 address 52 16 address 54 16 high-order byte address 51 16 address 53 16 address 55 16 note : at reset, the contents of the timer bi register are undefined. table 8.2.1 memory assignment of timer bi registers
7906 group user s manual rev.2.0 8-4 timer b 0 1 2 3 4 5 6 7 8.2.3 timer bi mode register figure 8.2.3 shows the structure of the timer bi mode register. the operating mode select bits are used to select the operating mode of timer bi. bits 2 to 7 have different functions according to the operating mode. these bits are described in the paragraph of each operating mode. 8.2.2 count start register this register is used to start and stop counting. one bit of this register corresponds to one timer. (this is the one-to-one relationship.) figure 8.2.2 shows the structure of the count start register 0. fig. 8.2.2 structure of count start register 0 8.2 block description fig. 8.2.3 structure of timer bi mode register count start register 0 (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : stop counting 1 : start counting bit name bit function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 operating mode select bits these bits have different functions according to the operating mode. timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : do not select. b1 b0 note: bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. 0 0 0 0 0 undefined 0 0 rw rw rw rw rw ro (note) rw rw bit name bit function at reset r/w
7906 group user s manual rev.2.0 8-5 timer b 0 1 2 3 7 to 4 8.2.4 timer bi interrupt control register figure 8.2.4 shows the structure of the timer bi interrupt control register. for details about interrupts, refer to ?hapter 6. interrupts. 8.2 block description fig. 8.2.4 structure of timer bi interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits are used to select a timer bi interrupt s priority level. when using timer bi interrupts, select the priority level from levels 1 through 7. when a timer bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl), so that the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable bit (i) = 0. ) to disable timer bi interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a timer bi interrupt request occurs. this bit is automatically cleared to 0 when the timer bi interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits interrupt request bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 note: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 0 0 0 undefined rw rw rw rw (note) bit name bit function at reset r/w
7906 group user s manual rev.2.0 8-6 timer b 8.2.5 port p2 direction register, port p5 direction register the input pins of timer bi are multiplexed with port p5 pins. by using the tb0 in /tb1 in /tb2 in pin select bit (see figure 8.2.5.), pin tb0 in /tb1 in /tb2 in can be allocated to the corresponding port p2 pin. when using pins p5 5 (p2 4 )/tb0 in , p5 6 (p2 5 )/tb1 in , p5 7 (p2 6 )/tb2 in as timer bi s input pins, be sure to clear the corresponding bits of the port direction register, which is multiplexed, to 0 in order to set these pins to the input mode. (see figure 8.2.6.) 8.2 block description port p2 pin function control register (address ae 16 ) 0 1 2 3 6 to 4 7 bit name bit function at reset r/w pin tb0 in select bit pin tb1 in select bit pin tb2 in select bit pin int 3 /rtp trg0 select bit (note) nothing is assigned. fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 : allocate pin tb2 in to p5 7 . 1 : allocate pin tb2 in to p2 6 . 0: allocate pin int 3 /rtp trg0 to p7 4 . 1: allocate pin int 3 /rtp trg0 to p2 7 . 0 : allocate pin tb0 in to p5 5 . 1 : allocate pin tb0 in to p2 4 . 0 : allocate pin tb1 in to p5 6 . 1 : allocate pin tb1 in to p2 5 . 0 0 0 0 undefined 0 rw rw rw rw rw note: when allocating pin int 3 /rtp trg0 to p7 4 , be sure the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 0 fig. 8.2.5 structure of port p2 pin function control register
7906 group user s manual rev.2.0 8-7 timer b corresponding pin bit 4 to 0 5 6 7 port p5 direction register (address d 16 ) functions at reset r/w nothing is assigned. pin tb0 in (pin int 5 /idw) (note 1) pin tb1 in (pin int 6 /idv) (note 2) pin tb2 in (pin int 7 /idu) (note 3) rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 notes 1: this applies when the tb0 in pin select bit (bit 0 at address ae 16 ) = 0. 2: this applies when the tb1 in pin select bit (bit 1 at address ae 16 ) = 0. 3: this applies when the tb2 in pin select bit (bit 2 at address ae 16 ) = 0. 4: the pins in ( ) are i/o pins of other internal peripheral devices, which are multiplexed with the corresponding port p5 pins. 0 : input mode 1 : output mode when using this pin as timer bi s input pin, be sure to clear the corresponding bit to 0. undefined 0 0 0 fig. 8.2.6 relationship between port p5 direction register, port p2 direction register, and timer bi? input pins 8.2.6 count source (in timer mode and pulse period/pulse width measurement mode) in the timer mode and pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5b 16 to 5d 16 ) are used to select the count source (f 2 , f 16 , f 64 , or f 512 ). (see figures 8.3.1 and 8.5.1.) 0 0 0 0 0 0 0 0 pin ta4 out pin ta4 in pin ta9 out pin ta9 in pin tb0 in (note 1) pin tb1 in (note 2) pin tb2 in (note 3) pin int 3 /rtp trg0 (note 4) port p2 direction register (address 8 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode 1 : output mode when using this pin as timer bi s input pin, be sure to clear the corresponding bit to 0. corresponding pin bit functions at reset r/w notes 1: this applies when the tb0 in pin select bit (bit 0 at address ae 16 ) = 1. 2: this applies when the tb1 in pin select bit (bit 1 at address ae 16 ) = 1. 3: this applies when the tb2 in pin select bit (bit 2 at address ae 16 ) = 1. 4: this applies when the int 3 /rtp trg0 pin select bit (bit 3 at address ae 16 ) = 1. 0 1 2 3 4 5 6 7 rw rw rw rw rw rw rw rw 8.2 block description
7906 group user s manual rev.2.0 8-8 timer b 8.3 timer mode in this mode, the timer counts an internally generated count source. table 8.3.1 lists the specifications of the timer mode. figure 8.3.1 shows the structures of the timer bi register and timer bi mode register in the timer mode. table 8.3.1 specifications of timer mode 8.3 timer mode item count source f i count operation division ratio count start condition count stop condition interrupt request occurrence timing tbi in pin s function read from timer bi register write to timer bi register specifications f 2 , f 16 , f 64 , or f 512 countdown when a counter underflow occurs, reload register s contents are re- loaded, and counting continues. when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter underflow occurs. programmable i/o port pin counter value can be read out. while counting is stopped when a value is written to the timer bi register, it is written to both of the reload register and counter. while counting is in progress when a value is written to the timer bi register, it is written only to the reload register. (transferred to the counter at the next reload timing.) 1 (n + 1) n: timer bi register s set value
7906 group user s manual rev.2.0 8-9 timer b 0 1 2 3 4 5 6 7 fig. 8.3.1 structures of timer bi register and timer bi mode register in timer mode 8.3 timer mode operating mode select bits these bits are invalid in timer mode. this bit is invalid in timer mode; its value is undefined at reading. count source select bits undefined 15 to 0 any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. rw b0 b7 b0 b7 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 00 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 x : it may be either 0 or 1. xx x 0 0 0 0 0 undefined 0 0 rw rw rw rw ro rw rw note: reading from or writing to this register must be performed in a unit of 16 bits. bit function at reset r/w bit name bit function at reset r/w x
7906 group user s manual rev.2.0 8-10 timer b 8.3.1 setting for timer mode figure 8.3.2 shows an initial setting example for registers relevant to the timer mode. note that when using interrupts, set up registers to enable the interrupts. for details, refer to ?hapter 6. interrupts. fig. 8.3.2 initial setting example for registers relevant to timer mode 8.3 timer mode count starts. b7 b0 count source select bit s 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 00 selecting timer mode and count source timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting count start bit to 1 b7 b0 count start register 0 (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit ? b7 b6 setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. ? : it may be either 0 or 1. selection of timer mode note : the counter divides the count source by (n + 1). setting division ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) ? ??
7906 group user s manual rev.2.0 8-11 timer b 8.3 timer mode 8.3.2 operation in timer mode ? when the count start bit is set to 1, the counter starts counting of the count source. ? when a counter underflow occurs, the reload register s contents are reloaded and counting continues. ? the timer bi interrupt request bit is set to 1 at the counter underflow in ? . the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. figure 8.3.3 shows an example of operation in the timer mode. fig. 8.3.3 example of operation in timer mode stops counting. restarts counting. ffff 16 n 0000 16 time count start bit timer bi interrupt request bit counter contents (hex.) cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. set to 1 by software. 1 / f i ? (n+1) f i : frequency of count source cleared to 0 by software. n : reload register s contents
7906 group user s manual rev.2.0 8-12 timer b [precautions for timer mode] [precautions for timer mode] while counting is in progress, by reading the timer bi register, the counter value can be read out at arbitrary timing. however, if the timer bi register is read at the reload timing shown in figure 8.3.4, the value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer bi register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 8.3.4 reading timer bi register 210 nn 1 counter value (hex.) 210 ffff n 1 read value (hex.) reload time n = reload register s contents
7906 group user s manual rev.2.0 8-13 timer b 8.4 event counter mode 8.4 event counter mode in this mode, the timer counts an external signal. table 8.4.1 lists the specifications of the event counter mode. figure 8.4.1 shows the structures of the timer bi register and the timer bi mode register in the event counter mode. table 8.4.1 specifications of event counter mode item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing tbi in pin s function read from timer bi register write to timer bi register specifications external signal input to the tbi in pin, or fx 32 (note 1) the count source s valid edge can be selected from the falling edge, the rising edge, and both of the falling and rising edges by software. countdown when a counter underflow occurs, reload register s contents are reloaded, and counting continues. when the count start bit is set to 1. when the count start bit is cleared to 0. when the counter underflow occurs. count source input pin (note 2) counter value can be read out. while counting is stopped when a value is written to the timer bi register, it is written to both of the reload register and counter. while counting is in progress when a value is written to the timer bi register, it is written only to the reload register. (transferred to the counter at the next reload timing.) (n + 1) 1 n: timer bi register s set value notes 1: only for timer b2, fx 32 can be selected. 2: when fx 32 is selected as the count source in timer b2, the tb2 in pin can be used as a programmable i/o port pin or as i/o pins of other internal peripheral devices, which are multiplexed.
7906 group user s manual rev.2.0 8-14 timer b 8.4 event counter mode fig. 8.4.1 structures of timer bi register and timer bi mode register in event counter mode operating mode select bits count polarity select bits this bit is invalid in event counter mode. this bit is invalid in event counter mode; its value is undefined at reading. these bits are invalid in event counter mode. rw rw rw rw ro rw rw 0 1 2 3 4 5 6 7 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 1 : event counter mode b1 b0 01 0 0 : count at falling edge of external signal 0 1 : count at rising edge of external signal 1 0 : count at both falling and rising edges of external signal 1 1 : do not select. (note) b3 b2 x : it may be either 0 or 1. note: when the timer b2 clock source select bit (bit 6 at address 63 16 ) = 1, be sure to fix these bits to 01 2 (count at the rising edge of the external signal). x xx 0 0 0 0 0 undefined 0 0 bit name bit function at reset r/w undefined 15 to 0 any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. rw b0 b7 b0 b7 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) note: reading from or writing to this register must be performed in a unit of 16 bits. bit function at reset r/w x
7906 group user s manual rev.2.0 8-15 timer b 8.4 event counter mode 8.4.1 count source for timer b2 in the event counter mode, a count source (an external signal into the tb2 in pin, or fx 32 ) can be selected by using the timer b2 clock source select bit. (see figure 8.4.2.) timers b0 and b1 count the external signals input to the tb0 in and tb1 in pins, respectively. when fx 32 is selected as the count source, the tb2 in pin serves as a programmable i/o port pin or as i/ o pins of other internal peripheral devices, which are multiplexed. fig. 8.4.2 structure of particular function select register 1 0 1 2 3 4 5 6 7 rw (note 2) rw (note 2) rw rw rw rw notes 1: at power-on reset, this bit becomes 0. at hardware reset or software reset, this bit retains the value just before reset. 2: even when 1 is written, the bit status will not change. 3: setting this bit to 1 must be performed just before execution of the wit instruction. also, after the wait state is termi- nated, this bit must be cleared to 0 immediately. (note 1) (note 1) 0 0 0 0 0 0 particular function select register 1 (address 63 16 ) b7 b6 b5 b4 b3 b2 b1 b0 bit name bit function at reset r/w stp-instruction-execution status bit wit-instruction-execution status bit fix this bit to 0. system clock stop select bit at wit (note 3) fix this bit to 0. the value is 0 at reading. timer b2 clock source select bit (valid in event counter mode.) the value is 0 at reading. 0 : normal operation. 1 : during execution of stp instruction 0 : normal operation. 1 : during execution of wit instruction 0 : external signal input to the tb2 in pin is counted. 1 : fx 32 is counted. 0 : in the wait mode, system clock f sys is active. 1 : in the wait mode, system clock f sys is inactive. 0 0
7906 group user? manual rev.2.0 8-16 timer b 8.4 event counter mode 8.4.2 setting for event counter mode figure 8.4.3 shows an initial setting example for registers relevant to the event counter mode. note that when using interrupts, set up to enable the interrupts. for details, refer to section ?hapter 6. interrupts. fig. 8.4.3 initial setting example for registers relevant to event counter mode note: the counter divides the count source by (n + 1). setting division ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) count starts. b7 b0 0 0 : count at falling edge of external signal. 0 1 : count at rising edge of external signal. 1 0 : count at both of falling and rising edges of external signal. 1 1 : do not selected. 01 selecting event counter mode and count polarity timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting count start bit to 1 b7 b0 count start register 0 (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit b3 b2 setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. ?? ? : it may be either 0 or 1. selection of event counter mode count polarity select bits ? ? selecting clock source b7 b0 particular function select register 1 (address 63 16 ) timer b2 clock source select bit 0 : count an external signal input to the tb2 in pin 1 : count fx 32 timers b0 and b1 timer b2 0 setting port p2 direction register b7 b0 p2 direction register (address 8 16 ) clear the corresponding bit to 0. (note 2) pin tb0 in pin tb1 in pin tb2 in when a pin is allocated to a port p2 pin (note 1) setting port p5 direction register b7 b0 p5 direction register (address d 16 ) clear the corresponding bit to 0. (note 2) pin tb0 in pin tb1 in pin tb2 in when a pin is allocated to a port p5 pin (note 1) notes 1: by using bits 0 to 2 of the port p2 pin function control register (address ae 16 ), be sure to set the pin allocation. (see figure 8.2.5.) 2: when fx 32 is selected as the count source in timer b2 (in other words, when bit 6 at address 63 16 = 1), this setting is unnecessary.
7906 group user s manual rev.2.0 8-17 timer b 8.4 event counter mode 8.4.3 operation in event counter mode ? when the count start bit is set to 1, the counter starts counting of the count source. ? when a counter underflow occurs, the reload register s contents are reloaded, and counting continues. ? the timer bi interrupt request bit is set to 1 at the counter underflow in ? . the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. figure 8.4.4 shows an example of operation in the event counter mode. fig. 8.4.4 example of operation in event counter mode stops counting. restarts counting . ffff 16 n 0000 16 time count start bit timer bi interrupt request bit counter contents (hex. ) cleared to 0 when interrupt request is accepted or cleared to 0 by software. set to 1 by software. starts counting. cleared to 0 by software. set to 1 by software. n : reload ragister s contents
7906 group user s manual rev.2.0 8-18 timer b [precautions for event counter mode] [precautions for event counter mode] while counting is in progress, by reading the timer bi register, the counter value can be read out at arbitrary timing. however, if the timer bi register is read at the reload timing shown in figure 8.4.5, a value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer bi register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 8.4.5 reading timer bi register 21 0 nn 1 counter value (hex.) 21 0 ffff n 1 read value (hex.) reload time n = reload register s contents
7906 group user s manual rev.2.0 8-19 timer b 8.5 pulse period/pulse width measurement mode 8.5 pulse period/pulse width measurement mode in this mode, the timer measures an external signal s pulse period or pulse width. tables 8.5.1 and 8.5.2 list the specifications of the pulse period/pulse width measurement mode. figure 8.5.1 shows the structures of the timer bi register and timer bi mode register in the pulse period/pulse width measurement mode. (1) pulse period measurement the timer measures the pulse period of the external signal that is input to the tbi in pin. (2) pulse width measurement the timer measures the pulse width ( l level and h level widths) of the external signal that is input to the tbi in pin. table 8.5.1 specifications of pulse period/pulse width measurement mode (when counter clear type is selected) item count source f i count operation count start condition count stop condition interrupt request occurrence timing tbi in pin s function read from timer bi register write to timer bi register timer bi overflow flag: this bit is used to identify the source of an interrupt request occurrence. notes 1: no interrupt request occurs when the first valid edge is input after the counter starts counting. 2: when using timer b2, make sure that the timer b2 clock source select bit (see figure 8.4.2.) to 0. 3: the value read out from the timer bi register is undefined in the period after the counter starts counting until the second valid edge is input. specifications f 2 , f 16 , f 64 , or f 512 countup counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues after clearing the counter value to 0000 16 . when the count start bit is set to 1. when the count start bit is cleared to 0. when a valid edge of measurement pulse is input (note 1) . when a counter overflow occurs (the timer bi overflow flag is set to 1 simultaneously.) measurement pulse input pin (note 2) the value obtained by reading the timer bi register is the reload register s contents (measurement result) (note 3) . invalid
7906 group user s manual rev.2.0 8-20 timer b item count source f i count operation count start condition count stop condition interrupt request occurrence timing tbi in pin s function read from timer bi register write to timer bi register timer bi overflow flag: this bit is used to identify the source of an interrupt request occurrence. notes 1: no interrupt request occurs when the first valid edge is input after the counter starts counting. 2: when using timer b2, make sure that the timer b2 clock source select bit (see figure 8.4.2.) = 0. 3: the value read out from the timer bi register is undefined in the period after the counter starts counting until the second valid edge is input. specifications f 2 , f 16 , f 64 , or f 512 countup counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues. when a counter overflow occurs, the timer bi overflow flag is set to 1, and counting continues after clearing the counter value to 0000 16 . when the count start bit is set to 1. when the count start bit is cleared to 0. when a valid edge of measurement pulse is input (note 1) . measurement pulse input pin (note 2) the value obtained by reading the timer bi register is the reload register s contents (measurement result) (note 3) . invalid table 8.5.2 specifications of pulse period/pulse width measurement mode (when free-run type is selected) 8.5 pulse period/pulse width measurement mode
7906 group user s manual rev.2.0 8-21 timer b 8.5 pulse period/pulse width measurement mode fig. 8.5.1 structures of timer bi register and timer bi mode register in pulse period/pulse width measurement mode 0 1 2 3 4 5 6 7 note: reading from this register must be performed in a unit of 16 bits. undefined 15 to 0 the measurement result of pulse period or pulse width is read out. ro timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) operating mode select bits measurement mode select bits count-type select bit timer bi overflow flag (note) count source select bits b7 b6 b5 b4 b3 b2 b1 b0 1 0 : pulse period/pulse width measurement mode b1 b0 10 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement (interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : do not select. b3 b2 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 note: the timer bi overflow flag is cleared to 0 when a value is written to the timer bi mode register with the count start bit = 1. this flag cannot be set to 1 by software. 0 : no overflow 1 : overflowed 0 0 0 0 0 undefined 0 0 rw rw rw rw rw ro rw rw b0 b7 b0 b7 (b15) (b8) bit function at reset r/w bit name bit function at reset r/w 0 : counter clear type 1 : free-run type
7906 group user s manual rev.2.0 8-22 timer b 8.5 pulse period/pulse width measurement mode 8.5.1 setting for pulse period/pulse width measurement mode figure 8.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 6. interrupts. fig. 8.5.2 initial setting example for registers relevant to pulse period/pulse width measurement mode count starts. b7 b0 measurement mode select bits 10 selecting pulse period/pulse width measurement mode and each function timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) (note 1) setting count start bit to 1 b7 b0 count start register 0 (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit b3 b2 setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. count source select bits b7 b6 timer bi overflow flag (note 2) 0: no overflow 1: overflowed 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement 1 1 : do not select. 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 notes 1: when using timer b2, be sure to clear the timer b2 clock source select bit (see figure 8.4.2.) to 0. 2: the timer bi overflow flag is a read-only bit. this bit is undefined after reset. when a value is written to the timer bi mode register with the count start bit = 1, this bit will be cleared to 0. 3: by using bits 0 to 2 of the port p2 pin function control register (address ae 16 ), be sure to set the pin allocation. (see figure 8.2.5.) selection of pulse period/pulse width measurement mode count-type select bit 0: counter clear type 1: free-run type setting port p2 direction register b7 b0 port p2 direction register (address 8 16 ) clear the coressponding bit to 0. pin tb0 in pin tb1 in pin tb2 in when a pin is allocated to a port p2 pin (note 3) setting port p5 direction register b7 port p5 direction register (address d 16 ) clear the coressponding bit to 0. pin tb0 in pin tb1 in pin tb2 in b0 when a pin is allocated to a port p5 pin (note 3)
7906 group user s manual rev.2.0 8-23 timer b 8.5 pulse period/pulse width measurement mode 8.5.2 operation in pulse period/pulse width measurement mode when counter clear type is selected ? when the count start bit is set to 1, the counter starts counting of the count source. ? the counter value is transferred to the reload register when a valid edge of the measurement pulse is detected. (refer to section (1) pulse period/pulse width measurement. ) ? the counter value is cleared to 0000 16 after the transfer in ? , and the counter continues counting. ? the timer bi interrupt request bit is set to 1 when the counter value is cleared to 0000 16 in ? ( note ). the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. ? the timer repeats operations ? to ? above. note: no timer bi interrupt request occurs when the first valid edge is input after the counter starts counting. when free-run type is selected ? when the count start bit is set to 1, the counter starts counting of the count source. ? the counter value is transferred to the reload register when a valid edge of the measurement pulse is detected. (refer to section (1) pulse period/pulse width measurement. ) ? the timer bi interrupt request bit is set to 1 after the transfer in ? (note) . the interrupt request bit remains set to 1 until the interrupt request is accepted or until the interrupt request bit is cleared to 0 by software. the counter continues counting with the counter value kept. ? when a counter overflow occurs, the timer bi overflow flag is set to 1, and counting continues after clearing the counter value to 0000 16 . at this time, the timer bi interrupt request bit does not change. ? the timer repeats operations ? to ? above. note: no timer bi interrupt request occurs when the first valid edge is input after the counter starts counting. (1) pulse period/pulse width measurement the measurement mode select bits (bits 3 and 2 at addresses 5b 16 and 5d 16 ) specify whether the pulse period of an external signal is measured or its pulse width is done. table 8.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. make sure that the measurement pulse interval from the falling edge to the rising edge, and vice versa are two cycles of the count source or more. additionally, use software to identify whether the measurement result indicates the h level width or the l level width. table 8.5.3 relationship between measurement mode select bits and pulse period/pulse width measurements b3 0 0 1 pulse period/pulse width measurement pulse period measurement pulse width measurement measurement interval (valid edges) from falling edge to falling edge (falling edges) from rising edge to rising edge (rising edges) from falling edge to rising edge, and vice versa (falling and rising edges) b2 0 1 0
7906 group user s manual rev.2.0 8-24 timer b (2) timer bi overflow flag when counter clear type is selected a timer bi interrupt request occurs when a measurement pulse s valid edge is input or when a counter overflow occurs. the timer bi overflow flag is used to identify the source of the interrupt request occurrence, that is, whether it is an overflow occurrence or a valid edge input. the timer bi overflow flag is set to 1 at an overflow occurrence. accordingly, the source of the interrupt request occurrence is identified by checking the timer bi overflow flag in the interrupt routine. when a value is written to the timer bi mode register after the next count timing of the count source with the count start bit = 1, the timer bi overflow flag will be cleared to 0 . the timer bi overflow flag is a read-only bit. use the timer bi interrupt request bit to detect the overflow timing. do not use the timer bi overflow flag for this detection. when free-run type is selected the timer bi overflow flag is set to 1 at an overflow occurrence. (at this time, no timer bi interrupt request is generated.) accordingly, whether a counter overflow occurs between valid edges is identified by checking the timer bi overflow flag in the interrupt routine owing to a valid edge input. when a value is written to the timer bi mode register after the next count timing of the count source with the count start bit = 1, the timer bi overflow flag will be cleared to 0 . the timer bi overflow flag is a read-only bit. figure 8.5.3 shows the processing example of a timer bi interrupt when a measurement pulse s valid edge is detected by the timer bi interrupt request. 8.5 pulse period/pulse width measurement mode fig. 8.5.3 processing example of timer bi interrupt when free-run count type is selected rti 0 1 timer bi interrupt (note 1) measured value is read out. (note 2) timer bi overflow flag ? timer bi overflow flag is cleared to 0. (note 3) processing with overflow processing without overflow notes 1: the valid edge of the measurement pulse is detected. 2: be sure to read out the timer bi register. 3: after the timer bi overflow flag is set to 1 , be sure to wait for one cycle of the count source to elapse. then, write a value to the timer bi mode register.
7906 group user s manual rev.2.0 8-25 timer b 8.5 pulse period/pulse width measurement mode fig. 8.5.4 operation examples during pulse period measurement (when counter clear type is selected) figures 8.5.4 and 8.5.5 show the operation examples during the pulse period measurement; figures 8.5.6 and 8.5.7 show the operation examples during the pulse width measurement. ? ? ? count source measurement pulse ffff 16 undefined value counter contents (hex.) 0000 16 reload register counter transfer timing timing at which counter is cleared to 0000 16 transferred (undefined value) transferred (measured value) time count start bit request bit timer bi interrupt timer bi overflow flag cleared to 0 when interrupt request is accepted or cleared to 0 by software. ? the above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. ? counter is initialized by completion of measurement. ? counter overflows. undefined cleared to 0 by software.
7906 group user s manual rev.2.0 8-26 timer b 8.5 pulse period/pulse width measurement mode fig. 8.5.5 operation examples during pulse period measurement (when free-run count type is selected) ? ? count source measurement pulse ffff 16 undefined value counter contents (hex.) 0000 16 transferred (undefined value) transferred (measured value) reload register counter transfer timing timing at which counter is cleared to 0000 16 count start bit request bit timer bi interrupt cleared to 0 when interrupt request is accepted or cleared to 0 by software. ? counter is initialized by the first valid edge. ? counter overflows. ? the above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. cleared to 0 by software. undefined time
7906 group user s manual rev.2.0 8-27 timer b 8.5 pulse period/pulse width measurement mode fig. 8.5.6 operation example during the pulse width measurement (when counter clear type is selected) ? ? ?? ? count source measurement pulse ffff 16 undefined value counter contents (hex.) 0000 16 time transferred (undefined value) transferred (measured value) transferred (measured value) transferred (measured value) reload register counter transfer timing timing at which counter is cleared to 0000 16 count start bit request bit timer bi interrupt timer bi overflow flag ? counter is initialized by completion of measurement. ? counter overflows. cleared to 0 when interrupt request is accepted or cleared to 0 by software. cleared to 0 by software. undefined
7906 group user s manual rev.2.0 8-28 timer b 8.5 pulse period/pulse width measurement mode fig. 8.5.7 operation example during the pulse width measurement (when free-run count type is selected) ? ? count source measurement pulse ffff 16 counter contents (hex.) undefined value 0000 16 time transferred (undefined value) transferred (measured value) transferred (measured value) transferred (measured value) reload register counter transfer timing timing at which counter is cleared to 0000 16 count start bit request bit timer bi interrupt timer bi overflow flag ? counter is initialized by the first valid edge. ? counter overflows. cleared to 0 when interrupt request is accepted or cleared to 0 by software. cleared to 0 by software. undefined
7906 group user s manual rev.2.0 8-29 timer b [precautions for pulse period/pulse width measurement mode] [precautions for pulse period/pulse width measurement mode] 1. when the counter clear type is selected, a timer bi interrupt request is generated by one of the following sources: valid edge input of measured pulse counter overflow when an overflow generates an interrupt request, the timer bi overflow flag will be set to 1. 2. when the free-run type is selected, the timer bi interrupt request is generated only by the valid edge input of the pulse to be measured. 3. after reset, the timer bi overflow flag is undefined. when a value is written to the timer bi mode register after the next count timing of the count source with the count start bit = 1, this flag will be cleared to 0. 4. an undefined value is transferred to the reload register at the first valid edge input after the count start. in this case, no timer bi interrupt request will occur. 5. the counter value at count start is undefined. therefore, there is a possibility that a counter overflow occurs immediately after the counting starts. in this case, the timer bi overflow flag becomes 1 ; and when the counter clear type is selected, a timer bi interrupt request is generated. 6. if the contents of the measurement mode select bits are changed after the count start, the timer bi interrupt request bit is set to 1. when the value, which has been set in these bits before, are written again, the timer bi interrupt request bit will not change. 7. when using timer b2, be sure to clear the timer b2 clock source select bit (bit 6 at address 63 16 ) to 0. 8. if the input signal to the tbi in pin is affected by noise, etc., there is a possibility that the counter cannot perform the exact measurement. we recommend to verify, by software, that the measurement values are within a constant range.
7906 group user s manual rev.2.0 8-30 timer b [precautions for pulse period/pulse width measurement mode] memorandum
chapter 9 pulse output port mode 9.1 overview 9.2 block description 9.3 setting of pulse output port mode 9.4 pulse output port mode operation [precautions for pulse output port mode]
pulse output port mode 7906 group user? manual rev.2.0 9-2 9.1 overview 9.1 overview the pulse output port mode function is used to change the output levels at several pins simultaneously with the following: each underflow occurrence in timer a or each valid edge input of an external signal. the pulse output port mode has two operation modes as listed in table 9.1.1. table 9.1.1 overview of pulse output port mode note: the pulse output pins, where pulse width modulation is to be applied, determine the timer to be used. ? 6 pins rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 : timer a1 ? 2 groups of 3 pins ?rtp0 0 to rtp0 2 : timer a1 ?rtp0 3 , rtp1 0 , rtp1 1 : timer a2 ? 3 groups of 2 pins ?rtp0 0 , rtp0 1 : timer a1 ?rtp0 2 , rtp0 3 : timer a2 ?rtp1 0 , rtp1 1 : timer a4 operation mode pulse mode 0 pulse mode 1 pulse output pins pulse output trigger register where output data is to be set pulse width modulation negative pulse output pulse-output- cutoff signal input pin rtp0 0 to rtp0 3 (p6 0 to p6 3 ) underflow occurrence in timer a0 or valid edge of signal input to pin rtp trg0 three-phase output data register 0 (bits 0 to 3) available (timer a1 used) available p6out cut (input of falling edge) rtp1 0 , rtp1 1 (p6 4 , p6 5 ) underflow of timer a3 three-phase output data register 1 (bits 4, 5) not available available rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 (p6 0 to p6 3 , p6 4 , p6 5 ) underflow of timer a0 or valid edge of signal input to pin rtp trg0 three-phase output data register 0 (bits 0 to 5) available (note) (timers a1, a2, a4 used) available p6out cut (input of falling edge)
pulse output port mode 7906 group user? manual rev.2.0 9-3 9.2 block description fig. 9.2.1 block diagram in pulse output port mode 9.2 block description figure 9.2.1 shows the block diagram in the pulse output port mode. also, the pulse-output-port-mode- relevant registers are described below. in the pulse output port mode and three-phase waveform mode, the following registers are used in common: the waveform output mode register (address a6 16 ), three-phase output data register 0 (address a8 16 ), and three-phase output data register 1 (address a9 16 ). after the pulse output port mode is set by the waveform output select bits (bits 2 to 0 at address a6 16 ), be sure to set the relevant registers. note that, when not using the pulse output port mode and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 to 0 at address a6 16 ) to ?00 2 . bits 0 through 3 of three- phase output data register 0 (address a8 16 ) pulse width modulation output of timer a1 bits 4, 5 of three-phase output data register 0 (address a8 16 ) or bits 4, 5 of three-phase output data register 1 (address a9 16 ) aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa data bus (even-numbered) b0 b1 b2 b0 b1 b2 b3 b4 b5 pulse output mode select bit (bit 3 at address a6 16 ) pulse width modulation timer select bits (bits 5, 4 at address a6 16 ) rtp1 0 rtp1 1 pulse output polarity select bit (bit 3 at address a9 16 ) rtp0 3 d q d q d q pulse width modulation enable bits 0 through 2 (bits 0 through 2 at address a9 16 ) d q d q aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa data bus (odd-numbered) waveform output control bit 0 (bit 6 at address a6 16 ) reset waveform output control bit 1 (bit 7 at address a6 16 ) reset pulse width modulation output of timer a2 pulse width modulation output of timer a4 t d q rtp0 1 rtp0 2 d q r t d q d q d q r rtp0 0 t d q aaaaaaa a aaaaa a a aaaaa a a aaaaa a a aaaaa a a aaaaa a a aaaaa a aaaaaaa pulse width modulation circuit p6out cut timer a0 pulse output triggger select bits (bits 7, 6 at address a8 16 ) rtp trg0 timer a3
pulse output port mode 7906 group user s manual rev.2.0 9-4 9.2 block description 9.2.1 waveform output mode register figure 9.2.2 shows the structure of the waveform output mode register (in pulse output port mode). fig. 9.2.2 structure of waveform output mode register (in pulse output port mode) (1) waveform output select bits (bits 2 to 0) these bits are used to select whether a pin serves as a programmable i/o port pin or a pulse output pin. table 9.2.1 lists the functions of the waveform output select bits. table 9.2.1 functions of waveform output select bits port: this serves as a programmable i/o port pin or timer i/o pin. rtp: this serves as a pulse output pin regardless of the contents of the corresponding port direction register. note: this is selected by the pulse output mode select bit (bit 3 at address a6 16 ). pulse mode 0 (note) pulse mode 1 (note) 000 b2 b1 b0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port port port port rtp rtp rtp port rtp rtp 001 010 011 do not select. do not select. p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 0 1 2 3 4 5 6 7 waveform output select bits (note) pulse output mode select bit pulse width modulation timer select bits waveform output control bit 0 waveform output control bit 1 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 bit name bit waveform output mode register (address a6 16 ) function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 when pulse mode 0 is selected, 0: rtp1 0 , rtp1 1 : pulse outputs are disabled. 1: rtp1 0 , rtp1 1 : pulse outputs are enabled. when pulse mode 1 is selected, fix this bit to 0. see table 9.2.1. see table 9.2.2. 0 : pulse mode 0 1 : pulse mode 1 when pulse mode 0 is selected, 0 : rtp0 0 to rtp0 3 : pulse outputs are disabled. 1 : rtp0 0 to rtp0 3 : pulse outputs are enabled. when pulse mode 1 is selected, 0 : rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 : pulse outputs are disabled. 1 : rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 : pulse outputs are enabled. note: when not using the pulse output port mode and three-phase waveform mode, be sure to fix these bits to 000 2 .
pulse output port mode 7906 group user s manual rev.2.0 9-5 9.2 block description (2) pulse output mode select bit (bit 3) this bit is used to select the type of the pulse output port mode: pulse mode 0 or pulse mode 1. (3) pulse width modulation timer select bits (bits 5 and 4) these bits are used to select the type of the pulse width modulation. table 9.2.2 lists the functions of the pulse width modulation timer select bits. (4) waveform output control bit 0 (bit 6) pulse mode 0 when this bit is set to 1, pulse output from pins rtp1 0 and rtp1 1 becomes enabled. when this bit is cleared to 0, pins rtp1 0 and rtp1 1 enter the floating state. pulse mode 1 fix this bit to 0. (5) waveform output control bit 1 (bit 7) pulse mode 0 when this bit is set to 1, pulse output from pins rtp0 0 to rtp0 3 becomes enabled. when this bit is cleared to 0, pins rtp0 0 to rtp0 3 enter the floating state. pulse mode 1 when this bit is set to 1, pulse output from pins rtp0 0 to rtp0 3 , rtp1 0 , and rtp1 1 becomes enabled. when this bit is cleared to 0, pins rtp0 0 to rtp0 3 , rtp1 0 , and rtp1 1 enter the floating state. when a falling edge is input to pin p6out cut , this bit becomes 0. (see figure 9.2.8.) table 9.2.2 functions of pulse width modulation timer select bits note: the pulse width modulation cannot be applied to pins rtp1 0 and rtp1 1 . pulse mode 0 (note) pulse mode 1 00 b5 b4 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 01 10 11 do not select. do not select. timer a1 timer a1 timer a2 timer a1 timer a2 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 timer a1 do not select. do not select. timer a4
pulse output port mode 7906 group user s manual rev.2.0 9-6 9.2 block description 9.2.2 three-phase output data registers 0, 1 figure 9.2.3 shows the structures of three-phase output data registers 0, 1 (in the pulse output port mode). fig. 9.2.3 structures of three-phase output data registers 0, 1 (in pulse output port mode) 0 1 2 3 4 5 7, 6 rw rw rw rw rw rw rw 0 0 0 0 0 0 0 bit name bit three-phase output data register 0 (address a8 16 ) function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 : l level output 1 : h level output note: invalid in pulse mode 0. rtp0 0 pulse output data bit rtp0 1 pulse output data bit rtp0 2 pulse output data bit rtp0 3 pulse output data bit rtp1 0 pulse output data bit (valid in pulse mode 1.) (note) rtp1 1 pulse output data bit (valid in pulse mode 1.) (note) pulse output trigger select bits 0 : l level output 1 : h level output 0 0 : underflow of timer a0 0 1 : falling edge of input signal to pin rtp trg0 1 0 : rising edge of input signal to pin rtp trg0 1 1 : both falling and rising edges of input signal to pin rtp trg0 b7 b6 three-phase output data register 1 (address a9 16 ) pulse width modulation enable bit 0 pulse width modulation enable bit 1 pulse width modulation enable bit 2 pulse output polarity select bit rtp1 0 pulse output data bit (valid in pulse mode 0) (note) rtp1 1 pulse output data bit (valid in pulse mode 0) (note) x 0 1 2 3 4 5 6 7 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 bit name bit function at reset r/w 0 : positive 1 : negative 0 : no pulse width modulation by timer a1 1 : pulse width modulation by timer a1 b7 b6 b5 b4 b3 b2 b1 b0 0 : no pulse width modulation by timer a2 1 : pulse width modulation by timer a2 0 : no pulse width modulation by timer a4 1 : pulse width modulation by timer a4 0 : l level output 1 : h level output x x: it may be either 0 or 1. note: invalid in pulse mode 1. invalid in pulse output port mode.
pulse output port mode 7906 group user s manual rev.2.0 9-7 9.2 block description (1) rtp0 0 to rtp0 3 pulse output data bits (bits 0 to 3 at address a8 16 ) each time when a pulse output trigger is generated, the contents written to these bits are output from the corresponding pulse output pins (note). the pulse output trigger can be selected by the pulse output trigger select bits (bits 7, 6 at address a8 16 ). (2) rtp1 0 , rtp1 1 pulse output data bits (bits 4, 5 at address a8 16 ) these bits are valid in pulse mode 1. each time when a pulse output trigger is generated, the contents written to these bits are output from the corresponding pulse output pins (note). the pulse output trigger can be selected by the pulse output trigger select bits (bits 7, 6 at address a8 16 ). these bits are invalid in pulse mode 0. (3) pulse output trigger select bits (bits 7, 6 at address a8 16 ) the pulse output trigger can be selected from an internal trigger and an external trigger. when using an external trigger (input signal to pin rtp trg0 ), be sure to clear the corresponding bit of the direction register of the port, which is multiplexed with pin rtp trg0 , in order to set this port pin for the input mode. (4) pulse width modulation enable bits 0 to 2 (bits 0 to 2 at address a9 16 ) these bits are used to select the pins, where the pulse width modulation is to be applied. synchronous with a pulse output trigger, the contents of these bits become valid. table 9.2.3 lists the pulse-width- modulation-relevant bits. (5) pulse output polarity select bit (bit 3 at address a9 16 ) when this bit = 0, the data corresponding to the contents which have been set in the rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 pulse output data bits are output from pins rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 . when this bit = 1, the contents which have been set in the rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 pulse output data bits are reversed (in other words, pulses with the negative polarity are generated here.); and then, these pulses with the negative polarity are output from pins rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 . (6) rtp1 0 , rtp1 1 pulse output data bits (bits 4, 5 at address a9 16 ) these bits are valid in pulse mode 0. each time when an underflow occurs in timer a3, the contents which have been written to these bits are output from the corresponding pulse output pins (note) . these bits are invalid in pulse mode 1. note: the output level at a pulse output pin is undefined in the period from when data is written to these bits until the first occurrence of a pulse output trigger. if it is necessary to avoid this state, perform processing of avoiding undefined output before starting pulse output in figure 9.3.2.
pulse output port mode 7906 group user s manual rev.2.0 9-8 9.2 block description ? ? ? ? 1 ? ? ? ? 1 ? ? 1 ? 1 1 ? 1 ? ? 1 pulse output pins where pulse width modulation is to be applied (timers used for pulse width modulation) pulse mode 0 pulse width modu- lation timer select bits (bits 5, 4 at address a6 16 ) pulse width modu- lation enable bit 2 (bit 2 at address a9 16 ) pulse width modu- lation enable bit 1 (bit 1 at address a9 16 ) pulse width modu- lation enable bit 0 (bit 0 at address a9 16 ) rtp0 3 to rtp0 0 (timer a1) rtp1 1 , rtp1 0 , rtp0 3 to rtp0 0 (timer a1) rtp1 1 , rtp1 0 , rtp0 3 (timer a2) rtp0 2 to rtp0 0 (timer a1) rtp1 1 , rtp1 0 (timer a4) rtp0 3 , rtp0 2 (timer a2) rtp0 1 , rtp0 0 (timer a1) 00 00 01 10 x: it may be either 0 or 1. table 9.2.3 pulse-width-modulation-related bits 4 pins 6 pins in a unit of 3 pins in a unit of 2 pins pulse mode 1
pulse output port mode 7906 group user s manual rev.2.0 9-9 9.2 block description fig. 9.2.4 structure of port p2 pin function control register 9.2.3 port p2 direction register, port p7 direction register figure 9.2.4 shows the structure of the port p2 pin function control register; figure 9.2.5 shows the relationship between the port p2/p7 direction register and pulse output trigger input pins. the allocation of the pulse output trigger input pin can be changed by the pin int 3 /rtp trg0 select bit. when using pin p7 4 (p2 7 )/rtp trg0 as a pulse output trigger input pin, be sure to clear the corresponding bit of the direction register of the port, which is multiplexed with pin rtp trg0 , in order to set this port pin for the input mode. port p2 pin function control register (address ae 16 ) 0 1 2 3 6 to 4 7 bit name bit function at reset r/w pin tb0 in select bit pin tb1 in select bit pin tb2 in select bit pin int 3 /rtp trg0 select bit (note) nothing is assigned. fix this bit to 0. b7 b6 b5 b4 b3 b2 b1 b0 0 : allocate pin tb2 in to p5 7 . 1 : allocate pin tb2 in to p2 6 . 0: allocate pin int 3 /rtp trg0 to p7 4 . 1: allocate pin int 3 /rtp trg0 to p2 7 . 0 : allocate pin tb0 in to p5 5 . 1 : allocate pin tb0 in to p2 4 . 0 : allocate pin tb1 in to p5 6 . 1 : allocate pin tb1 in to p2 5 . 0 0 0 0 undefined 0 rw rw rw rw rw note: when allocating pin int 3 /rtp trg0 to p7 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 0
pulse output port mode 7906 group user s manual rev.2.0 9-10 9.2 block description fig. 9.2.5 relationship between port p2/p7 direction register and pulse output trigger input pins corresponding pin bit 0 1 2 3 4 7 to 5 port p7 direction register (address 11 16 ) function at reset r/w 0 0 0 0 0 undefined rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 pin an 0 pin an 1 pin an 2 pin an 3 /da 0 pin rtp trg0 (pin an 4 /da 1 /int 3 ) (note 1) nothing is assigned. 0 : input mode 1 : output mode when using this pin as a pulse output trigger input pin, be sure to clear the corresponding bit to 0. corresponding pin bit 0 1 2 3 4 5 6 7 port p2 direction register (address 8 16 ) functions at reset r/w pin ta4 out pin ta4 in pin ta9 out pin ta9 in pin tb0 in (note 1) pin tb1 in (note 2) pin tb2 in (note 3) pin rtp trg0 (pin int 3 ) (note 4) 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode 1 : output mode when using this pin as a pulse output trigger input pin, be sure to clear the corresponding bit to 0. notes 1: this applies when the pin tb0 in select bit (bit 0 at address ae 16 ) = 1. 2: this applies when the pin tb1 in select bit (bit 1 at address ae 16 ) = 1. 3: this applies when the pin tb2 in select bit (bit 2 at address ae 16 ) = 1. 4: this applies when the pin int 3 /rtp trg0 select bit (bit 3 at address ae 16 ) = 1. 5: ( ) shows the i/o pin of another internal peripheral device which is multiplexed. notes 1: this applies when the pin int 3 /rtp trg0 select bit (bit 3 at address ae 16 ) = 0. 2: ( ) shows the i/o pin of another internal peripheral device which is multiplexed.
pulse output port mode 7906 group user s manual rev.2.0 9-11 9.2 block description 9.2.4 timers a0 to a4 timers a0 and a3 are used as control registers; each generates a pulse output trigger. when using timers a0 and a3, be sure to use them in the timer mode. (refer to section ?.3 timer mode. ) when performing the pulse width modulation, be sure to use timers a1, a2, a4 in the pulse width modulation mode. (refer to section ?.6 pulse width modulation (pwm) mode. ) note that, from pin p2 0 /ta4 out , a pwm pulse by timer a4 is output. when it is unnecessary to output a pwm pulse, be sure to clear bit 2 of the timer a4 mode register (address 5a 16 ) to 0. at this time, pin p2 0 can be used as a programmable i/o port pin. figure 9.2.6 shows the structure of the timer a0 and a3 mode registers (in the pulse output port mode); figure 9.2.7 shows the structures of the timer a1, a2, a4 mode registers (in the pulse output port mode with pulse width modulation used). fig. 9.2.6 structure of timer a0 and a3 mode registers (in pulse output port mode) bit name bit 0 1 2 3 4 5 6 7 timer a0 mode register (address 56 16 ) timer a3 mode register (address 59 16 ) functions at reset r/w fix these bits to 000000 2 in the pulse output port mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw see table 7.2.3. 00 0 00
pulse output port mode 7906 group user s manual rev.2.0 9-12 9.2 block description fig. 9.2.7 structures of timer a1, a2, a4 mode registers (in pulse output port mode with pulse width modulation used) rw rw rw rw rw rw rw rw bit name bit 0 1 2 3 4 5 6 7 timer a1 mode register (address 57 16 ) timer a2 mode register (address 58 16 ) functions at reset r/w fix these bits to 00011 2 in the pulse output port mode. 16/8-bit pwm mode select bit count source select bits b7 b6 b5 b4 b3 b2 b1 b0 11 0 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 0 0 0 0 0 0 0 see table 7.2.3. rw rw rw rw rw rw rw rw bit name bit 0 1 2 3 4 5 6 7 timer a4 mode register (address 5a 16 ) functions at reset r/w fix these bits to 11 2 in the pulse output port mode. pulse output function select bit fix these bits to 00 2 in the pulse output port mode. 16/8-bit pwm mode select bit count source select bits b7 b6 b5 b4 b3 b2 b1 b0 11 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 0 0 0 0 0 0 0 see table 7.2.3. 0 : no pulse output (ta4 out pin functions as a programmable i/o port pin.) 1 : pulse output (ta4 out pin functions as a pwm pulse output pin.) 0 0 0 0
pulse output port mode 7906 group user? manual rev.2.0 9-13 9.2 block description fig. 9.2.8 relationship between p6out cut input, waveform output control bit 1, and pulse output pin 9.2.5 pin p6out cut (pulse-output-cutoff signal input pin) when a falling edge is input to pin p6out cut , the waveform output control bit 1 (bit 7 at address a6 16 ) becomes ??and the pulse output pins enter the floating state. (in other words, pulse output becomes disabled.) the pulse output pins where pulse output is to be inactive depend on the pulse output mode. ?pulse mode 0: rtp0 0 to rtp0 3 ?pulse mode 1: rtp0 0 to rtp0 3 , rtp1 0 , rtp1 1 when restarting pulse output after the pulse output becomes inactive, be sure to return the input level at pin p6out cut to ??level; and then, be sure to set the waveform output control bit 1 to ?.?when the input level at pin p6out cut is ??level, the waveform output control bit 1 cannot be ?. also, at this time, bits 0 through 5 of the port p6 direction register (address 10 16 ) become ?00000 2 .?(refer to section ?.2.3 pin p6out cut /int 4 . ) therefore, if it is necessary to switch port pins p6 0 through p6 5 to port output pins, be sure to do as follows: ? return the input level at pin p6out cut to ??level. ? write data to the port p6 register (address e 16 )? bits, corresponding to the port p6 pins which will output data. ? set the port p6 direction register? bits, corresponding to the port p6 pins in ? , to ??in order to set these port pins to the output mode. when the input level at pin p6out cut is ??level, no bit of the port p6 direction register can be ?. figure 9.2.8 shows the relationship between the p6out cut input, waveform output control bit 1, and pulse output pin. note that, when not making the pulse output inactive by using pin p6out cut , be sure to connect pin p6out cut to vcc via a resistor. p6out cut input programmable i/o port floating waveform output control bit 1 (bit 7 at address a6 16 ) pulse output pin pulse output pulse output floating ?? selection of pulse output port mode (selected by bit s 3 to 0 at address a6 16 ) ? ? ? when the pulse output port mode is selected, the pulse outpit pins become floating. ? the pulse is output by writing of 1 with the input level at pin p6out cut = h. ? when a falling edge is input to pin p6out cut , this bit becomes 0.
pulse output port mode 7906 group user s manual rev.2.0 9-14 9.3 setting of pulse output port mode fig. 9.3.1 initial setting example for registers relevant to pulse output port mode (in pulse mode 1) (1) 9.3 setting of pulse output port mode figures 9.3.1 to 9.3.5 show an initial setting example for registers relevant to the pulse output port mode, where an underflow of timer a0 is used as a pulse output trigger (in pulse mode 1). note that when using interrupts, set up to enable the interrupts. for details, refer to ?hapter 6. interrupts. continue to figure 9.3.2. selecting pulse output mode and selecting each function b0 waveform output mode register (address a6 16 ) b7 0 pulse mode 1 00 pulse widh modulation timer select bits see table 9.2.2. waveform output control bit 0 fix this bit to 0 in pulse mode 1. waveform output control bit 1 pulse output disabled ? pulse output pins are floating until the pulse output becomes enabled. 11 0
pulse output port mode 7906 group user s manual rev.2.0 9-15 9.3 setting of pulse output port mode fig. 9.3.2 initial setting example for registers relevant to pulse output port mode (in pulse mode 1) (2) from preceding figure 9.3.1 this processing can be omitted when the system is not affected by the undefined output. continue to figure 9.3.3. processing of avoiding undefined output before starting pulse output (note) b0 timer a0 mode register (address 56 16 ) b7 selection of count source f 2 00000 00 b7 a value of 0000 16 is set. b0 b7 b0 (b15) (b8) 00 16 00 16 b0 timer a0 interrupt control register (address 75 16 ) b7 0 interrupt disabled 000 no interrupt request b0 count start register 0 (address 40 16 ) b7 timer a0 count start bit 1 : start counting when an underflow occurs in timer a0, the contents of three-phase output data register 0 are output from the filp-flop. (pulse output pins are floating until the pulse output becomes enabled.) b0 count start register 0 (address 40 16 ) b7 timer a0 count start bit 0 : stop counting b0 three-phase output data register 0 (address a8 16 ) b7 rtp0 0 rtp0 1 rtp0 2 rtp0 3 rtp1 0 rtp1 1 x : it may be either 0 or 1. initial output data is set. b0 three-phase output data register 1 (address a9 16 ) b7 pulse width modulation enable bit 0 pulse width modulation enable bit 1 pulse width modulation enable bit 2 see table 9.2.3. timer a0 register (addresses 47 16 and 46 16 ) pulse output polarity select bit 0 : positive 1 : negative ???? 0 00 pulse output trigger select bits underflow of timer a0
pulse output port mode 7906 group user s manual rev.2.0 9-16 9.3 setting of pulse output port mode fig. 9.3.3 initial setting example for registers relevant to pulse output port mode (in pulse mode 1) (3) from preceding figure 9.3.2 continue to figure 9.3.4. selecting pulse output data, pulse output mode, pulse width modulation b0 timer a0 mode register (address 56 16 ) b7 count source select bits see table 7.2.3. 000 00 b7 a value in the range from 0000 16 to ffff 16 (n) is set. b0 b7 b0 (b15) (b8) 00 16 00 16 b0 timer a0 interrupt control register (address 75 16 ) b7 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. 0 no interrupt request b0 three-phase output data register 0 (address a8 16 ) b7 rtp0 0 rtp0 1 rtp0 2 rtp0 3 rtp1 0 rtp1 1 x : it may be either 0 or 1. the output data is set. b0 three-phase output data register 1 (address a9 16 ) b7 pulse width modulation enable bit 0 pulse width modulation enable bit 1 pulse width modulation enable bit 2 see table 9.2.3. timer a0 register (addresses 47 16 and 46 16 ) pulse output polarity select bit 0 : positive 1 : negative ???? 0 00 pulse output trigger select bits underflow of timer a0 setting of timer a0
pulse output port mode 7906 group user s manual rev.2.0 9-17 9.3 setting of pulse output port mode fig. 9.3.4 in itial setting example for registers relevant to pulse output port mode (in pulse mode 1) (4) b7 b0 count source select bits see table 7.2.3. 11 timer aj mode register (j = 1, 2, 4) (addresses 57 16 , 58 16 , 5a 16 ) 16/8-bit pwm mode select bit 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator setting of pwm pulse period and h level width b7 b0 a value in the range from 0000 16 to fffe 16 (n) is set. (b15) (b8) b7 b0 timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) however, if n = 0000 16 , the pulse width modulator does not operate and pin taj out pin outputs l level. at this time, no timer aj interrupt request occurs. when 16-bit pulse width modulator b7 b0 a value in the range from 00 16 to ff 16 (m) is set. (b15) (b8) b7 b0 timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) when 8-bit pulse width modulator a value in the range from 00 16 to fe 16 (n) is set. 2 1 f i 16 however, if n = 00 16 , the pulse width modulator does not operate and pin taj out pin outputs l level. at this time, no timer aj interrupt request occurs. h level width = f i : frequency of count source period = ? when operating as 16-bit pulse width modulator n f i (m + 1)(2 1) f i ? when operating as 8-bit pulse width modulator h level width = f i : frequency of count source period = 8 n (m + 1) f i from preceding figure 9.3.3 continue to figure 9.3.5. when pulse width modulation is not performed when pulse width modulation is performe d j = 1, 2 : fix this bit to 0. j = 4 : when not using pin ta4 out (in other words, when using pin p2 0 as a programmable i/o port pin), clear this bit to 0. 0 0
pulse output port mode 7906 group user s manual rev.2.0 9-18 9.3 setting of pulse output port mode fig. 9.3.5 initial setting example for registers relevant to pulse output port mode (in pulse mode 1) (5) from preceding figure 9.3.4 setting count start bit to 1. b0 count start register 0 (address 40 16 ) b7 timer a0 count start bit timer a1 count start bit pulse output starts after an underglow of timer a0. enabling pulse output b0 waveform output mode register (address a6 16 ) b7 waveform output control bit 1 pulse output enabled ? when pulse output becomes enabled, the initial output data is output from pulse output pins. timer a2 count start bit timer a3 count start bit 1
pulse output port mode 7906 group user s manual rev.2.0 9-19 9.4 pulse output port mode operation 9.4 pulse output port mode operation 9.4.1 pulse output trigger (1) rtp0 0 to rtp0 3 in pulse mode 0, pulse mode 1 the pulse output trigger can be selected from an internal trigger and an external trigger. when the pulse output trigger select bits (bits 7, 6 at address a8 16 ) = 00 2 , an internal trigger is selected; when these bits = 01 2 , 10 2 , or 11 2 , an external trigger is selected. a trigger occurs at an underflow of timer a0. this trigger occurrence can be confirmed by using the timer a0 interrupt request bit. a trigger occurs at a valid edge input to pin rtp trg0 (note) . this trigger occurrence can be confi- rmed by using the int 3 interrupt request bit. table 9.4.1 lists the setting of int 3 according to valid edges. also, the allocation of pin rtp trg0 can be changed by the pin int 3 /rtp trg0 select bit (bit 3 at address ae 16 ). be sure to clear the port direction register s bit, corresponding to pin rtp trg0 , to 0 in order to set the port pin to the input mode. note: this is set by the pulse output trigger select bits (bits 7, 6 at address a8 16 ). (2) rtp1 0 , rtp1 1 in pulse mode 0 the pulse output trigger is an internal trigger. a trigger occurs at an underflow of timer a3. this trigger occurrences can be confirmed by using the timer a3 interrupt request bit. note: refer to section 6.10 external interrupts. valid edge input to pin rtp trg0 setting of int 3 (note) falling rising falling and rising falling (edge sense) rising (edge sense) falling and rising (edge sense): used alternately table 9.4.1 setting of int 3 according to valid edges
pulse output port mode 7906 group user s manual rev.2.0 9-20 9.4 pulse output port mode operation fig. 9.4.1 example of pulse output port mode operation (1) 9.4.2 operation at internal trigger ? when the timer ai (i = 0, 3) count start bit is set to 1, the counter starts counting of a count source. ? the contents of the pulse output data bits of three-phase output data registers 0, 1 are output from the corresponding pulse output pins at each underflow of timer ai. while the pulse width modulation is selected, the pulse width modulation is performed for h level output. the timer reloads the contents of the reload register and continues counting. ? the timer ai interrupt request bit is set to 1 when the counter underflows in ? . the interrupt request bit retains 1 until the interrupt request is accepted or it is cleared to 0 by software. ? write the next output data into three-phase output data registers 0, 1 during a timer ai interrupt routine (or after the confirmation of a timer ai interrupt request occurrence.) figures 9.4.1 to 9.4.3 show examples of pulse output port mode operations. contents of bits 3 to 0 of three-phase output data register 0 rtp0 0 output rtp0 1 output rtp0 2 output rtp0 3 output timer a0 interrupt request bit n 0000 16 undefined ? 2 undefined ? 2 undefined ? 2 undefined ? 2 0011 2 0110 2 1100 2 1001 2 ? 1 ? 1 ? 1 ? 1 ? 3 ? 3 ? 3 starts counting starts pulse outputting ? 1 ? 1 ? 3 ffff 16 n : reloaded value timer a0 s counter contents (hex.) ? 1 : written by software ? 2 : when avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure processing of avoiding undefined output before starting pulse output in figure 9.3.2. ? 3 : cleared to 0 by an interrupt request acceptance or cleared by software. the above applies when the following conditions are satisfied: pulse mode 0 selected rtp0 0 to rtp0 3 selected no pulse width modulation positive polarity
pulse output port mode 7906 group user s manual rev.2.0 9-21 9.4 pulse output port mode operation fig. 9.4.2 example of pulse output port mode operation (2) timer a0 interrupt request bit n 0000 16 undefined ? 2 undefined ? 2 undefined ? 2 undefined ? 2 0011 2 0110 2 1100 2 1001 2 ? 1 ? 1 ? 1 ? 1 ? 3 ? 3 ? 3 starts counting starts pulse outputting ? 1 timer a0 s counter contents ? 1 ? 3 ffff 16 n : reloaded value (hex.) contents of bits 3 to 0 of three-phase output data register 0 rtp0 0 output rtp0 1 output rtp0 2 output rtp0 3 output ? 1 : written by software ? 2 : when avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure processing of avoiding undefined output before starting pulse output in figure 9.3.2. ? 3 : cleared to 0 by an interrupt request acceptance or cleared by software. the above applies when the following conditions are satisfied: pulse mode 0 selected rtp0 0 to rtp0 3 selected no pulse width modulation negative polarity
pulse output port mode 7906 group user s manual rev.2.0 9-22 9.4 pulse output port mode operation fig. 9.4.3 example of pulse output port mode operation (3) n 0000 16 undefined ? 2 undefined ? 2 undefined ? 2 undefined ? 2 ? 3 ? 3 ? 3 starts counting starts pulse outputting ? 1 timer a0 s counter contents ? 3 ffff 16 n : reloaded value 001100 2 011000 2 110000 2 100001 2 ? 1 ? 1 ? 1 ? 1 ? 1 pwm signal by timer a1 pwm signal by timer a2 pwm signal by timer a4 undefined ? 2 undefined ? 2 (hex.) contents of bits 5 to 0 of three-phase output data register 0 rtp0 0 output rtp0 1 output rtp0 2 output rtp0 3 output timer a0 interrupt request bit rtp1 0 output rtp1 1 output ? 1 : written by software ? 2 : when avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure processing of avoiding undefined output before starting pulse output in figure 9.3.2. ? 3 : cleared to 0 by an interrupt request acceptance or cleared by software. the above applies when the following conditions are satisfied: pulse mode 1 selected pulse width modulation applied (in a unit of 2 pins; timers a1, a2, and a4 are used.) positive polarity
pulse output port mode 7906 group user s manual rev.2.0 9-23 9.4 pulse output port mode operation 9.4.3 operation at external trigger ? each time when a valid edge of a signal input to pin rtp trg0 (note) is input, the contents of the pulse output data bits of three-phase output data register 0 are output from the corresponding pulse output pins. when the pulse width modulation is selected, the pulse width modulation is applied to h level output. ? the int 3 interrupt request bit is set to 1 when a valid edge ( ? ) is input. (refer to section 9.4.1 pulse output trigger. ) the interrupt request bit retains 1 until the interrupt request is accepted or it is cleared by software. ? write the next output data into three-phase output data register 0 during an int 3 interrupt routine (or after the confirmation of an int 3 interrupt request occurrence). note: this is set by the pulse output trigger select bits (bits 7, 6 at address a8 16 ).
pulse output port mode 7906 group user s manual rev.2.0 9-24 [precautions for pulse output port mode] [precautions for pulse output port mode] 1. when using the pulse output port mode, be sure to set the relevant registers after the pulse output port mode is set by the waveform output select bits (bits 2 to 0 at address a6 16 ). when not using the pulse output port mode and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 to 0 at address a6 16 ) to 000 2 . 2. when performing the pulse width modulation, be sure to use timers a1, a2, a4 in the pulse width modulation mode. (refer to section 7.6 pulse width modulation (pwm) mode. ) note that, from pin p2 0 /ta4 out , a pwm pulse by timer a4 is output. when it is unnecessary to output a pwm pulse, be sure to clear bit 2 of the timer a4 mode register (address 5a 16 ) to 0. at this time, pin p2 0 can be used as a programmable i/o port pin. 3. note that, when not making the pulse output inactive by input of a falling edge to pin p6out cut , be sure to connect pin p6out cut to vcc via a resistor.
chapter 10 three-phase waveform mode 10.1 overview 10.2 block description 10.3 three-phase mode 0 10.4 three-phase mode 1 10.5 three-phase waveform output fixation 10.6 position-data-retain function [precautions for three-phase waveform mode]
three-phase waveform mode 7906 group user? manual rev.2.0 10-2 10.1 overview the three-phase waveform mode serves as follows: three-phase waveforms (3 positive waveforms and 3 negative waveforms) are output from the three-phase waveform output pins. the three-phase waveform mode consists of ?hree-phase mode 0?and ?hree-phase mode 1. table 10.1.1 lists the specifications of the three-phase waveform mode, table 10.1.2 lists the comparison of operations in three-phase mode 0 and 1, and figure 10.1.1 shows the comparison of waveforms in three- phase mode 0 and 1. table 10.1.1 specifications of three-phase waveform mode table 10.1.2 comparison of operations in three-phase mode 0 and 1 6 pins (u, u, v, v, w, w) p6out cut (input of falling edge) three-phase mode 0 a timer a3 interrupt request occurs at each timer a3 underflow. three-phase mode 1 a timer a3 interrupt request occurs at each second timer a3 underflow or forth one. timers a0 through a2 (used in the one-shot pulse mode) ?timer a0 : w- and w-phase waveform control ?timer a1 : v- and v-phase waveform control ?timer a2 : u- and u-phase waveform control timer a3 (used in the timer mode) ?output period control saw-tooth-wave mo- dulation output triangular wave mo- dulation output fixed level output dead-time timer is used. see table 10.2.1. item specifications three-phase waveform output pins three-phase-waveform-output- forcibly-cutoff signal input pin operation modes timer to be used three-phase waveform period output waveform and output width dead time (width) ? 2 to ? 65535 ? 2 (note) 1 f 1 1 f 4096 to ? 65535 (note) 1 f 1 1 f 4096 to ? 65536 1 f 1 1 f 4096 each of the u, v, w phases is fixed to an arbitrary level. each of the u, v, w phases is fixed to the reversed level of the corresponding positive phase (the u, v, w phases). note: this value does not include the dead time. each timer a3 underflow each timer uses one register. ? by software, the output polarity can be set to the output polarity set buffer of the u, v, or w phases. if necessary, the contents of each output polarity set buffer are reversed by software. three-phase mode 0 three-phase mode 1 timer a3 interrupt request occurrence interval timers a0 through a2 output polarity each second timer a3 underflow or forth one is selected by software. each timer uses two registers alternately. by software, the output polarity can be set to the three-phase output polarity set buffer. at each period, the contents of the three- phase output polarity set buffer are reversed by hardware. 10.1 overview
three-phase waveform mode 7906 group user? manual rev.2.0 10-3 10.1 overview fig. 10.1.1 comparison of waveforms in three-phase mode 0 and 1 timer a3 underflow signal timer a3 interrupt request signal timer a2 one-shot pulse output phase u phase u three-phase mode 0 : triangular wave modulation by software at each timer a3 interrupt, waveform output polarity is reversed. data is written to timer a2. waveform output polarity is reversed by hardware. three-phase mode 1 : triangular wave modulation timer a3 interrupt request signal timer a2 one-shot pulse output phase u phase u by software at each timer a3 interrupt, data is written to timer a2 register. data is written to timer a2 1 register. contets of timer a2 1 register contets of timer a2 register contets of timer a2 register contets of timer a2 1 register note: this applies when a timer a3 interrupt request occurs at each second timer a3 underflow. timer a3 interrupt request signal timer a2 one-shot pulse output phase u phase u three-phase mode 0 : saw-tooth-wave modulation by software at each timer a3 interrupt, data is written to timer a2.
three-phase waveform mode 7906 group user s manual rev.2.0 10-4 10.2 block description figure 10.2.1 shows the block diagram of the three-phase waveform mode, and explanation of registers relevant to the three-phase waveform mode is described below. the following registers are common to the pulse output port mode and three-phase waveform mode: waveform output mode register (address a6 16 ) three-phase output data register 0 (address a8 16 ) three-phase output data register 1 (address a9 16 ) when using the three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through 0 at address a6 16 ) to 100 2 , and then, set the relevant registers. when not using the pulse output port mode and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through 0 at address a6 16 ) to 000 2 . 10.2 block description fig. 10.2.1 block diagram of three-phase waveform mode dq t d q output polarity set toggle flip-flop 2 0 1 d q t r timer a3 (16) (timer mode) timer a2 reload timer a2 1 timer a2 counter (16) u-phase output polarity set buffer (bit 5 at address a9 16 ) t interval control d q r d q r timer a1 reload timer a1 1 timer a1 counter (16) v-phase output polarity set buffer (bit 4 at address a9 16 ) t timer a0 reload timer a0 1 timer a0 counter (16) w-phase output polarity set buffer (bit 3 at address a8 16 ) t three-phase output polarity set buffer (bit 3 at address a6 16 ) interrupt validity output select bit (bit 5 at address a9 16 ) three-phase mode select bit (bit 4 at address a6 16 ) d q output polarity set toggle flip-flop 0 0 1 d q output polarity set toggle flip-flop 1 0 1 reset interrupt request interval set bit (bit 4 at address a9 16 ) 1 0 reset q d r reset timer a3 interrupt request signal (one-shot pulse mode) (one-shot pulse mode) (one-shot pulse mode) reload register dead-time timer (8) t dead-time timer (8) t f 2 f 4 f 8 clock-source-of-dead-time-timer select bits (bits 7, 6 at address a8 16 ) d q t dead-time timer (8) t d q r reset p6out cut u v w u v w waveform output control bit (bit 7 at address a6 16 ) u-phase output fix bit (bit 2 at address a8 16 ) dq trigger generating circuit s r q t q v-phase output fix bit (bit 1 at address a8 16 ) dq dq t trigger generating circuit s r q t q w-phase output fix bit (bit 0 at address a8 16 ) dq dq t trigger generating circuit s r q t q u-phase output control circuit v-phase output control circuit w-phase output control circuit d q t d q t d q t d q t d q t u-phase output fix polarity set bit (bit 2 at address a9 16 ) w-phase output fix polarity set bit (bit 0 at address a9 16 ) v-phase output fix polarity set bit (bit 1 at address a9 16 ) 1/2 1/2 idu t q d t q d t q d b2 idv idw b1 b0 data bus (even-numbered) bits 2 through 0 of position- data-retain function control register (address aa 16 ) circuit
three-phase waveform mode 7906 group user s manual rev.2.0 10-5 10.2.1 waveform output mode register figure 10.2.2 shows the structure of the waveform output mode register (the three-phase waveform mode). note that writing to bits 0 through 6 of this register must be performed when the counting in timers a0 through a3 is halts. 10.2 block description fig. 10.2.2 structure of waveform output mode register (three-phase waveform mode) waveform output mode register (address a6 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 x waveform output select bits (note 1) three-phase output polarity set buffer (valid in three-phase mode 1) (note 2) three-phase mode select bit dead-time timer trigger select bit (note 3) waveform output control bit bit name bit function at reset r/w rw rw rw rw rw rw rw rw x: it may be either 0 or 1. notes 1: when not using the pulse output mode and three-phase waveform mode, be sure to fix these bits to 000 2 . 2: this bit is invalid in three-phase mode 0. 3: when the saw-tooth-wave modulation output is performed, be sure to fix this bit to 0. 4: writing to any of bits 0 to 6 must be performed while counting for timers a0 to a3 halts. 1 0 0 : three-phase waveform mode 0 : h output 1 : l output 0 : three-phase mode 0 1 : three-phase mode 1 0: both falling and rising edges of one-shot pulse for timers a0 to a2 1: only the falling edge of one-shot pulse for timers a0 to a2 0 : waveform output disabled 1 : waveform output enabled b0 b2 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 invalid in the three-phase waveform mode. b1
three-phase waveform mode 7906 group user s manual rev.2.0 10-6 10.2 block description (1) three-phase output polarity set buffer (bit 3) this bit serves as the buffer to set the output polarity of the three-phase waveform and is used in three-phase mode 1. (refer to section ?0.2.9 output polarity set toggle flip-flop. ) (2) three-phase mode select bit (bit 4) this bit is used to select three-phase mode 0 or 1. (3) dead-time timer trigger select bit (bit 6) this bit is used to select a trigger of the dead-time timer. the saw-tooth-wave modulation requires that this bit is fixed to 0. (4) waveform output control bit (bit 7) setting of this bit to 1 allows the three-phase waveform output from the three-phase waveform output pins. clearance of this bit to 0 makes the three-phase waveform output pins floating. when a falling edge is input to pin p6out cut , this bit becomes 0. (see figure 10.2.15.)
three-phase waveform mode 7906 group user s manual rev.2.0 10-7 10.2 block description 10.2.2 dead-time timer register figure 10.2.3 shows the structure of the dead-time timer register. the dead-time timer is used to count the time to prevent l level of positive waveform outputs from overlapping with l level of their negative waveform outputs. (this time is referred to as dead time. ) figure 10.2.4 shows the structure of the dead-time timer. fig. 10.2.3 structure of dead-time timer register fig. 10.2.4 structure of dead-time timer dead-time timer reload register dead-time timer dead-time timer dead-time timer trigger trigger trigger dead-time timer register (address a7 16 ) (common to 3 dead-time timers) timer a2 timer a1 timer a0 f 2 clock-source-of-dead-time-timer select bits (bits 7, 6 at address a8 16 ) 1/2 1/2 undefined 7 to 0 bit dead-time timer (address a7 16 ) function at reset r/w a value in the range from 00 16 to ff 16 can be set. wo b0 b7 note: use the movmb ( movm when m = 1) or stab ( sta when m = 1) instruction for writing to this register. additionally, make sure writing to this register does not overlap with a trigger-occurrence timing of the dead-time timer.
three-phase waveform mode 7906 group user s manual rev.2.0 10-8 10.2 block description when a certain value is written to the dead-time timer register, this value is written to the dead-time reload register. the m37906 has three dead-time timers, and they are independent each other. when a trigger is generated due to each of timers a0 through a2, the contents of the dead-time timer reload register are reloaded; and then, the selected count source is counted down. simultaneously, the one-shot pulse is output. a trigger is selected by the dead-time timer trigger select bit (bit 6 at address a6 16 ), and the count source is selected by the clock-source-of-dead-time-timer select bits (bits 7, 6 at address a8 16 ). when an underflow occurs, the counting becomes inactive. figure 10.2.5 shows the relationship between the dead-time timer s pulse and trigger, and table 10.2.1 lists the pulse width of the dead-time timer. table 10.2.1 pulse width of dead-time timer fig. 10.2.5 relationship between dead-time timer? pulse and trigger n: a value which is set in the dead-time timer (address a7 16 ) f i : the dead-time timer s clock source (f 2 , f 2 /2, f 2 /4) note: width of pulse starting from a re-trigger occurrence timing edge rising edge of timer ai one-shot pulse falling edge of timer ai one-shot pulse rising edge of timer ai one-shot pulse (re-trigger) falling edge of timer ai one-shot pulse (re-trigger) state at trigger input dead-time timer: inactive dead-time timer: active pulse width n : 00 16 trigger n : 01 16 through ff 16 1 f i 1 f i 1 f i 1 f i 1 f i 1 f i (note) (note) 258 ? 257 ? 257 ? (n+2) ? (n+1) ? (n+1) ? timer ai s one-shot pulse dead-time timer s pulse (reversed signal) timer ai s one-shot pulse dead-time timer s pulse (reversed signal) when dead-time timer trigger select bit = 0 timer ai s one-shot pulse when dead-time timer trigger select bit = 1 internal signal when re-triggering internal signal re-trigger re-trigger dead-time timer s pulse (reversed signal) internal signal
three-phase waveform mode 7906 group user s manual rev.2.0 10-9 10.2 block description 10.2.3 three-phase output data register 0 figure 10.2.6 shows the structure of the three-phase output data register 0 (the three-phase waveform mode). for bits 7 and 6, refer to section ?0.2.2 dead-time timer. fig. 10.2.6 structure of three-phase output data register 0 (three-phase waveform mode) (1) w-phase output fix bit (bit 0) setting of this bit to 1 fixes the output level at the w-phase waveform output pin to the level which is selected by the w-phase fixed output s polarity set bit (bit 0 at address a9 16 ); vice versa, the output level at the w-phase waveform output pin is reversed. (2) v-phase output fix bit (bit 1) setting of this bit to 1 fixes the output level at the v-phase waveform output pin to the level which is selected by the v-phase fixed output s polarity set bit (bit 1 at address a9 16 ); vice versa, the output level at the v-phase waveform output pin is reversed. (3) u-phase output fix bit (bit 2) setting of this bit to 1 fixes the output level at the u-phase waveform output pin to the level which is selected by the u-phase fixed output s polarity set bit (bit 2 at address a9 16 ); vice versa, the output level at the u-phase waveform output pin is reversed. (4) w-phase output polarity set buffer (bit 3) this bit serves as the buffer to set the w-phase output polarity and is used in three-phase mode 0. (refer to section ?0.2.9 output polarity set toggle flip-flop. ) three-phase output data register 0 (address a8 16 ) b7 b6 b5 b4 b3 b2 b1 b0 x x x: it may be either 0 or 1. note: this bit is invalid in three-phase mode 1. 0 0 : f 2 0 1 : f 2 /2 1 0 : f 2 /4 1 1 : do not select. w-phase output fix bit v-phase output fix bit u-phase output fix bit w-phase output polarity set buffer (valid in three-phase mode 0.) (note) clock-source-of-dead-time-timer select bits bit name bit 0 1 2 3 5, 4 6 7 function at reset r/w 0 0 0 0 0 0 0 rw rw rw rw rw rw rw 0 : released from output fixation 1 : output fixed 0 : released from output fixation 1 : output fixed 0 : released from output fixation 1 : output fixed b7 b6 0 : h output 1 : l output invalid in the three-phase waveform mode.
three-phase waveform mode 7906 group user s manual rev.2.0 10-10 10.2 block description 10.2.4 three-phase output data register 1 figure 10.2.7 shows the structure of the three-phase output data register 1 (the three-phase waveform mode). fig. 10.2.7 structure of three-phase output data register 1 (three-phase waveform mode) three-phase output data register 1 (address a9 16 ) b7 b6 b5 b4 b3 b2 b1 b0 x x 0 : h output 1 : l output 0 : an interrupt request occurs at each even-number- ed underflow of timer a3 1 : an interrupt request occurs at each odd-number- ed underflow of timer a3 w-phase fixed output s polarity set bit (note 1) v-phase fixed output s polarity set bit (note 2) u-phase fixed output s polarity set bit (note 3) v-phase output polarity set buffer (in three-phase mode 0) interrupt request interval set bit (in three-phase mode 1) u-phase output polarity set buffer (in three-phase mode 0) interrupt validity output select bit (in three-phase mode 1) 0 : h output 1 : l output 0 : every second time 1 : every forth time bit name bit 0 1 2 3 4 5 7, 6 function at reset r/w 0 : h output fixed 1 : l output fixed 0 : h output fixed 1 : l output fixed 0 : h output fixed 1 : l output fixed 0 0 0 0 0 0 0 rw rw rw rw rw rw rw x: it may be either 0 or 1. notes 1: valid when the w-phase output fix bit (bit 0 at address a8 16 ) = 1. be sure not to change the value during output of a fixed value. 2: valid when the v-phase output fix bit (bit 1 at address a8 16 ) = 1. be sure not to change the value during output of a fixed value. 3: valid when the u-phase output fix bit (bit 2 at address a8 16 ) = 1. be sure not to change the value during output of a fixed value. x invalid in the three-phase waveform mode. invalid in the three-phase waveform mode.
three-phase waveform mode 7906 group user s manual rev.2.0 10-11 10.2 block description (1) w-phase fixed output? polarity set bit (bit 0) clearance of this bit to 0 fixes the output level at the w-phase waveform output pin to h ; vice versa, setting of this bit to 1 fixes the output level at the w-phase waveform output pin to l. the output level at the w-phase waveform output pin is reversed. note that this bit is valid only when the w-phase output fix bit (bit 0 at address a8 16 ) = 1. (2) v-phase fixed output? polarity set bit (bit 1) clearance of this bit to 0 fixes the output level at the v-phase waveform output pin to h ; vice versa, setting of this bit to 1 fixes the output level at the v-phase waveform output pin to l. the output level at the v-phase waveform output pin is reversed. note that this bit is valid only when the v-phase output fix bit (bit 1 at address a8 16 ) = 1. (3) u-phase fixed output? polarity set bit (bit 2) clearance of this bit to 0 fixes the output level at the u-phase waveform output pin to h ; vice versa, setting of this bit to 1 fixes the output level at the u-phase waveform output pin to l. the output level at the u-phase waveform output pin is reversed. note that this bit is valid only when the u-phase output fix bit (bit 2 at address a8 16 ) = 1. (4) v-phase output polarity set buffer (bit 4) (in three-phase mode 0) this bit serves as the buffer to set the v-phase output polarity. (refer to section ?0.2.9 output polarity set toggle flip-flop. ) interrupt request interval set bit (bit 4) (in three-phase mode 1) clearance of this bit to 0 generates a timer a3 interrupt request at every second time; vice versa, setting of this bit to 1 generates a timer a3 interrupt request at every forth time. (refer to section ?0.4 three-phase mode 1. ) (5) u-phase output polarity set buffer (bit 5) (in three-phase mode 0) this bit serves as the buffer to set the u-phase output polarity. (refer to section ?0.2.9 output polarity set toggle flip-flop. ) interrupt validity output select bit (bit 5) (in three-phase mode 1) clearance of this bit to 0 generates a timer a3 interrupt request at every even-numbered underflow of timer a3; vice versa, setting of this bit to 1 generates a timer a3 interrupt request at every odd- numbered underflow of timer a3. (refer to section ?0.4 three-phase mode 1. )
three-phase waveform mode 7906 group user s manual rev.2.0 10-12 10.2 block description 10.2.5 position-data-retain function control register figure 10.2.8 shows the structure of the position-data-retain function control register. for details of the position-data-retain function, refer to section ?0.6 position-data-retain function. fig. 10.2.8 structure of position-data-retain function control register (1) w-phase position data retain bit (bit 0) this bit is used to retain the input level at pin idw. (2) v-phase position data retain bit (bit 1) this bit is used to retain the input level at pin idv. (3) u-phase position data retain bit (bit 2) this bit is used to retain the input level at pin idu. (4) retain-trigger polarity select bit (bit 3) this bit is used to select the trigger polarity to retain the position data. when this bit = 0, the falling edge of each positive phase is selected. when this bit = 1, the rising edge of each positive phase is selected. note: this register is valid only in the three-phase mode. bit name bit 0 1 2 3 7 to 4 position-data-retain function control register (address aa 16 ) function at reset r/w w-phase position data retain bit v-phase position data retain bit u-phase position data retain bit retain-trigger polarity select bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 undefined ro ro ro rw input level at pin idw is read out. 0 : l level 1 : h level input level at pin idv is read out. 0 : l level 1 : h level input level at pin idu is read out. 0 : l level 1 : h level 0 : falling edge of positive phase 1 : rising edge of positive phase
three-phase waveform mode 7906 group user? manual rev.2.0 10-13 10.2.6 port p5 direction register the position-data input pins are multiplexed with port p5 pin. when using these pins as position-data-input pins, clear the corresponding bits of the port p5 direction register to ??in order to set these port pins for the input mode. figure 10.2.9 shows the relationship between the port p5 direction register and position-data-input pins. 10.2 block description fig. 10.2.9 relationship between port p5 direction register and position-data-input pins 10.2.7 timers a0 through a2 each of timers a0 through a2 is used to control the output width of each phase, and these timers are used in the one-shot pulse mode. figure 10.2.10 shows the structure of timer a0/a1/a2 mode register (in the three-phase waveform mode). because the underflow signal of timer a3 serves as a trigger for timers a0 through a3, it is unnecessary to set the one-shot start bit to ?. note that, in three-phase mode 1, each of timers a0 through a2 has the following two registers: timer a0/ a1/a2 register (addresses 46 16 and 47 16 , 48 16 and 49 16 , 4a 16 and 4b 16 ) and timer a0 1 /a1 1 /a2 1 register (addresses d0 16 and d1 16 , d2 16 and d3 16 , d4 16 and d5 16 ). these two registers are used to control the output width. figure 10.2.11 shows the structures of the timer a0/a1/a2 mode register and timer a0 1 /a1 1 /a2 1 register. fig. 10.2.10 structure of timer a0/a1/a2 mode register (three-phase waveform mode) corresponding pin bit 4 to 0 5 6 7 port p5 direction register (address d 16 ) functions at reset r/w nothing is assigned. pin idw (pin int 5 /tb0 in ) pin idv (pin int 6 /tb1 in ) pin idu (pin int 7 /tb2 in ) rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 note: the pins in ( ) are i/o pins of other internal peripheral devices, which are multiplexed. 0 : input mode 1 : output mode when using this pin as a position-data input pin, be sure to clear the corresponding bit to ?. undefined 0 0 0 bit name bit 0 1 2 3 4 5 6 7 timer a0/a1/a2 mode register (addresses 56 16 to 58 16 ) function at reset r/w fix these bits to ?11010 2 ?in the three-phase waveform mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw see table 7.2.3. 01 0 11
three-phase waveform mode 7906 group user? manual rev.2.0 10-14 10.2 block description fig. 10.2.11 structures of timer a0/a1/a2 register and timer a0 1 /a1 1 /a2 1 register 10.2.8 timer a3 timer a3 is used to control the carrier? period of the whole three-phase waveform and is used in the timer mode. figure 10.2.12 shows the structure of the timer a3 mode register (the three-phase waveform mode). fig. 10.2.12 structure of timer a3 mode register (three-phase waveform mode) bit name bit 0 1 2 3 4 5 6 7 timer a3 mode register (address 59 16 ) function at reset r/w fix these bits to ?00000 2 ?in the three-phase waveform mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw 00 0 00 see table 7.2.3. undefined 15 to 0 any value in the range from ?000 16 ?to ?fff 16 ?can be set. assuming that the set value = n, the ??level width of the one-shot pulse is expressed as follows : wo b0 b7 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) b0 b7 (b15) (b8) f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. n f i . bit function at reset r/w timer a0 1 register (addresses d1 16 , d0 16 ) timer a1 1 register (addresses d3 16 , d2 16 ) timer a2 1 register (addresses d5 16 , d4 16 ) b0 b7 b0 b7 (b15) (b8) undefined 15 to 0 bit function at reset r/w any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the ??level width of the one-shot pulse is expressed as follows: n/f i . wo f i : frequency of a count source notes 1: use the movm or sta (stad) instruction for writing to this register. additionally, make sure writing to this register must be performed in a unit of 16 bits. 2: this register is valid only in three-phase mode 1 of the three-phase waveform mode.
three-phase waveform mode 7906 group user? manual rev.2.0 10-15 10.2 block description 10.2.9 output polarity set toggle flip-flop the output polarity set toggle flip-flops 0 through 2 are used to control the output polarity of the positive and negative phases of the three-phase waveform. in three-phase mode 0, values are set into the u-, v-, w-phase output polarity set buffer (bits 5 and 4 at address a9 16 and bit 3 at address a8 16 ). in three-phase mode 1, a value is set into the three-phase output polarity set buffer (bit 3 at address a6 16 ). these bits are transferred to the output polarity set toggle flip-flop at an underflow of timer a3. the contents of the output polarity set toggle flip-flop are reversed at the end of the timer a0/a1/a2 one- shot pulse. table 10.2.2 lists the relationship between the contents of the output polarity set toggle flip-flop and the output level, and figure 10.2.13 shows the operations of the output polarity set buffer and output polarity set toggle flip-flop. table 10.2.2 relationship between contents of output polarity set toggle flip-flop and output level fig. 10.2.13 operations of output polarity set buffer and output polarity set toggle flip-flop contents of output polarity set toggle flip-flop output level of positive phase output level of negative phase 0 1 h l l h timer a3 underflow signal internal signals timer a2 one-shot pulse contents of u-phase output polarity set buffer contents of output polarity set toggle-flip flop 2 reversed reversed reversed reversed trans- ferred from buffer 1 0 1 0 trans- ferred trans- ferred trans- ferred
three-phase waveform mode 7906 group user s manual rev.2.0 10-16 10.2 block description 10.2.10 three-phase waveform mode i/o pins when the three-phase waveform mode is selected, port p6 0 through p6 5 pins become the three-phase waveform output pins, pin p6out cut becomes the three-phase-waveform-output-forcibly-cutoff signal input pin. figure 10.2.14 shows the pins used in the three-phase waveform mode. 10.2.11 pin p6out cut (three-phase-waveform-output-forcibly-cutoff signal input pin) when a falling edge is input to pin p6out cut , the waveform output control bit (bit 7 at address a6 16 ) becomes 0 ; and then the three-phase waveform output pins enter the floating state. (in other words, the three-phase waveform output becomes inactive.) when restarting the three-phase waveform output after this output becomes inactive, be sure to return the input level at pin p6out cut to h ; and then, be sure to set the waveform output control bit to 1. when the input level at pin p6out cut is l, the waveform output control bit cannot be 1. also, at this time, bits 0 through 5 of the port p6 direction register (address 10 16 ) become 000000 2 . (refer to section ?.2.3 pin p6out cut /int 4 . ) therefore, if it is necessary to switch port pins p6 0 through p6 5 to the port output pins, be sure to do as follows: ? return the input level at pin p6out cut to h level. ? write data to the port p6 register (address e 16 ) s bits, corresponding to the port p6 pins which will output data. ? set the port p6 direction register s bits, corresponding to the port p6 pins in ? , to 1 in order to set these port pins to the output mode. when the input level at pin p6out cut is l, each bit of the port p6 direction register cannot be 1. figure 10.2.15 shows the relationship between the p6out cut input, waveform output control bit, and three- phase waveform output pin. note that, when not inactivating the three-phase waveform output by using pin p6out cut , be sure to connect pin p6out cut to vcc via a resistor. fig. 10.2.14 pins used in three-phase waveform mode fig. 10.2.15 relationship between p6out cut input, waveform output control bit, and three-phase waveform output pin m37906 u-phase waveform output v-phase waveform output w-phase waveform output u-phase waveform output v-phase waveform output w-phase waveform output three-phase-waveform-output- forcibly-cutoff signal input p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw u-phase position data input v-phase position data input w-phase position data input p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p6out cut /int 4 ? when the three-phase waveform mode is selected, the three-phase waveform output pins enter the floating state. ? due to writing of 1 when the input level at pin p6out cut = h, a pulse is output. ? due to an input of a falling edge to p6out cut , this bit becomes 0. programmable i/o port floating waveform output control bit (bit 7 at address a6 16 ) three-phase waveform output pin p6out cut input three-phase waveform output three-phase waveform output floating ?? three-phase waveform mode is selected (bit 2 through 0 at address a6 16 = 100 2 ) ? ?
three-phase waveform mode 7906 group user s manual rev.2.0 10-17 10.3 three-phase mode 0 10.3 three-phase mode 0 10.3.1 setting for three-phase mode 0 explanation of the triangular wave modulation output and saw-tooth-wave modulation output in three-phase mode 0 is described below. table 10.3.1 lists the differences between the triangular wave modulation output and the saw-tooth-wave modulation output (in view of software). table 10.3.1 differences between triangular wave modulation output and saw-tooth-wave modulation output (in view of software) figures 10.3.1 and 10.3.2 show an initial setting example for registers relevant to three-phase mode 0, figure 10.3.3 shows a data-updating example in three-phase mode 0. note that the initial output level at the three-phase waveform output pin is undefined. be sure to start the three-phase waveform output (in other words, the waveform output is enabled.) after the output level at the three-phase waveform output pin is stabilized. falling and rising edges of timers a0 through a2 not reversed. trigger of dead-time timer contents of output polarity set buffer falling edge of timers a0 through a2 reversed at each timer a3 interrupt request occurrence. triangular wave modulation output saw-tooth-wave modulation output
three-phase waveform mode 7906 group user s manual rev.2.0 10-18 10.3 three-phase mode 0 fig. 10.3.1 initial setting example for registers relevant to three-phase mode 0 (1) timers a0 through a3 are inactive. b7 b0 count start register 0 (address 40 16 ) 0 0 0 0 stops counting in timer a0. stops counting in timer a1. stops counting in timer a2. stops counting in timer a3. continues to the next page. b7 b0 setting of dead-time timer dead-time timer (address a7 16 ) a value in the range from 00 16 to ff 16 is set. b7 b0 setting of waveform output mode register waveform output mode register (address a6 16 ) 0 0 1 ? 0 dead-time timer trigger select bit 0 : falling and rising edges of one-shot pulse 1 : falling edge of one-shot pulse waveform outout is disabled. three-phase mode 0 0 ? ? : it may be either 0 or 1. b7 b0 setting of timers a0 through a2 to one-shot pulse mode timer a0/a1/a2 mode register (addresses 56 16 to 58 16 ) 1 11 0 0 count source select bits (see table 7.2.3.) setting of timer a3 to timer mode timer a3 mode register (address 59 16 ) b7 b0 0 0 0 0 0 0 0 b7 b0 setting of timer a0/a1/a2 interrupt request to disabled timer a0/a1/a2 interrupt control register (addresses 75 16 to 77 16 ) 0 0 0 0 no interrupt request interrupt disabled setting of period of timer a3 s carrier wave b7 b0 a value in the range from 0000 16 to ffff 16 is set. b7 (b8) (b15) b0 setting of output width of each phase of timers a0 through a2 b7 b0 a value in the range from 0000 16 to ffff 16 is set. b7 (b8) (b15) b0 timer a3 register (addresses 4d 16 , 4c 16 ) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) b7 b0 setting of three-phase output data register 0, 1 three-phase output data register 0 (address a8 16 ) v-phase output polarity set buffer 0 : h output 1 : l output 00 0 clock-source-of-dead-time-timer select bits 0 0 : f 2 0 1 : f 2 /2 1 0 : f 2 /4 b7 b6 u-phase output polarity set buffer 0 : h output 1 : l output released from w-phase output fixation. released from v-phase output fixation. released from u-phase output fixation. ? b7 b0 w-phase output polarity set buffer 0 : h output 1 : l output ? ? ? three-phase output data register 1 (address a9 16 ) ? : it may be either 0 or 1. ? ?? ? count source select bits (see table 7.2.3.) timer a3 interrupt priority level set to one of levels 1 through 7. b7 b0 setting of timer a3 interrupt priority level timer a3 interrupt control register (address 78 16 ) 0 no interrupt request
three-phase waveform mode 7906 group user s manual rev.2.0 10-19 10.3 three-phase mode 0 fig. 10.3.2 initial setting example for registers relevant to three-phase mode 0 (2) three-phase waveform output starts. continued from the preceding page. check whether the timer ai interrupt request bit is 1 or not. (note that the first one-shot pulse width of timer ai must be the maximum among those of timers a0 through a2.) ? the output level is stabilized. b7 b0 three-phase waveform output is enabled. waveform output mode register (address a6 16 ) 1 three-phase waveform output is enabled. internal output for stabilization of output level b7 b0 count start register 0 (address 40 16 ) 1 starts counting in timer a0. starts counting in timer a1. starts counting in timer a2. starts counting in timer a3. 111 waiting for the dead time, which was previously set, to elapse
three-phase waveform mode 7906 group user s manual rev.2.0 10-20 fig. 10.3.3 data-updating example in three-phase mode 0 w-phase output polarity set buffer 0 : h output 1 : l output timer a0/a1/a2 data calculation for the next time timer a3 interrupt saw-tooth-wave modulation triangular wave modulation interrupt processing is completed. setting of output width of each phase of timers a0 through a2 b7 b0 a value in the range from 0000 16 to ffff 16 is set. b7 (b8) (b15) b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) setting of u-,v-,w-phase output polarity set buffer : reversed b7 b0 three-phase output data register 0 (address a8 16 ) u-phase output polarity set buffer 0 : h output 1 : l output b7 b0 three-phase output data register 1 (address a9 16 ) bit 3 is reversed. bits 4 and 5 are reversed. v-phase output polarity set buffer 0 : h output 1 : l output 10.3 three-phase mode 0
three-phase waveform mode 7906 group user s manual rev.2.0 10-21 10.3.2 operation in three-phase wave mode 0 figure 10.3.4 shows a triangular wave modulation output example (three-phase mode 0), and figure 10.3.5 shows a saw-tooth-wave modulation output example (three-phase mode 0) ? when an underflow occurs in the timer a3 counter, a timer a3 interrupt request is generated; simultaneously, the one-shot pulse outputs of timer a0 through a2 are started. also, the contents of the output polarity set buffer of each phase are transferred to the output polarity set toggle flip-flop. in the case of the saw-tooth-wave modulation output, the one-shot pulse of the dead-time timer is output. also, each of the positive and negative waveform outputs is not allowed to become l level from h level until the reversed signal of the one-shot pulse output of the dead-time timer rises. ? the contents of the output polarity set toggle flip-flop are reversed at each falling edge of the one shot pulse output of timer a0/a1/a2. simultaneously, the one-shot pulse of the dead-time timer is output. ? each of the positive and negative waveform outputs is not allowed to become l level from h level until the reversed signal of the one-shot pulse output of the dead-time timer rises. ? in the case of the triangular wave modulation output, before an underflow occurs in the timer a3 counter again, be sure to write the next data to the output polarity set buffer of each phase. repeat procedures from ? through ? for the three-phase waveform output control. figure 10.3.6 shows the triangular wave modulation output model (for one period), and figure 10.3.7 shows the saw-tooth-wave modulation output model (for one period). 10.3 three-phase mode 0
three-phase waveform mode 7906 group user s manual rev.2.0 10-22 fig. 10.3.4 triangular wave modulation output example (three-phase mode 0) carrier wave timer a3 interrupt request timer a3 underflow signal ? 2 contents of timer a0/a1/a2 register one-shot pulse output of timer a0/a1/a2 ? 2 contents of u/v/w output polarity set buffer contents of output polarity set toggle flip-flop ? 2 reversed signal of pulse output of dead-time timer ? 2 positive waveform output negative waveform output ???? n 1 n 2 n 3 n 4 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 1/f i ? n 1 1/f i ? n 2 1/f i ? n 3 1/f i ? n 4 trans- ferred transferred trans- ferred transferred reversed rever- sed reversed ? 1 : written by software ? 2 : this is an internal signal, which cannot be read from the external. f i : count source of timer a0/a1/a2 10.3 three-phase mode 0
three-phase waveform mode 7906 group user s manual rev.2.0 10-23 fig. 10.3.5 saw-tooth wave modulation output example (three-phase mode 0) carrier wave timer a3 interrupt request timer a3 underflow signal ? 2 contents of timer a0/a1/a2 register one-shot pulse output of timer a0/a1/a2 ? 2 contents of u/v/w output polarity set buffer contents of output polarity set toggle flip-flop ? 2 reversed signal of pulse output of dead-time timer ? 2 positive waveform output negative waveform output ??? n 1 n 2 n 3 n 4 ? 1 ? 1 ? 1 ? 1 1/f i ? n 1 1/f i ? n 2 1/f i ? n 3 1/f i ? n 4 trans- ferred transferred trans- ferred transferred reversed reversed ? 1 : written by software ? 2 : this is an internal signal, which cannot be read from the external. f i : count source of timer a0/a1/a2 l reversed 10.3 three-phase mode 0
three-phase waveform mode 7906 group user s manual rev.2.0 10-24 fig. 10.3.6 triangular wave modulation output model (for one period) u v w u u v v w w timer a3 timer a2 timer a1 timer a0 carrier wave sine wave ? ? ? ? ? this is an internal signal, which cannot be read from the external. note: the dead time is executed. 10.3 three-phase mode 0
three-phase waveform mode 7906 group user? manual rev.2.0 10-25 10.3 three-phase mode 0 fig. 10.3.7 saw-tooth-wave modulation output model (for one period) u v w u u v v timer a2 timer a1 timer a0 w w timer a3 carrier wave sine wave ? ? this is an internal signal, which cannot be read from the external. ? ? ? note: the dead time is executed.
three-phase waveform mode 7906 group user s manual rev.2.0 10-26 10.4 three-phase mode 1 10.4 three-phase mode 1 10.4.1 setting for three-phase mode 1 in the triangular wave modulation, three-phase mode 1 is more efficiently controllable than three-phase mode 0. therefore, three-phase mode 1 can mitigates the software s load. figure 10.4.1 and figure 10.4.2 show an initial setting example of registers relevant to three-phase mode 1, and figure 10.4.3 shows a data-updating example in three-phase mode 1. note that the initial output level at the three-phase waveform output pin is undefined. be sure to start the three-phase waveform output (in other words, the waveform output is enabled.) after the output level at the three-phase waveform output pin is stabilized.
three-phase waveform mode 7906 group user s manual rev.2.0 10-27 10.4 three-phase mode 1 fig. 10.4.1 initial setting example for registers relevant to three-phase mode 1 (1) timers a0 through a3 are inactive. b7 b0 count start register 0 (address 40 16 ) 0 0 0 0 stops counting in timer a0. stops counting in timer a1. stops counting in timer a2. stops counting in timer a3. continues to the next page. note: the contents of the three-phase output polarity set buffer are reversed once before the output level is stabilized. therefore, at this time, be sure to set the reversed level of the level which the user desires to output. b7 b0 setting of dead-time timer dead-time timer (address a7 16 ) a value in the range from 00 16 to ff 16 is set. b7 b0 setting of waveform output mode register waveform output mode register (address a6 16 ) 0 0 1 ? 0 dead-time timer trigger select bit falling edge of one-shot pulse waveform output is disabled. three-phase mode 1 1 three-phase output polarity set buffer (note) 0 : h output 1 : l output ? : it may be either 0 or 1. 1 b7 b0 setting of three-phase output data register 0, 1 three-phase output data register 0 (address a8 16 ) interrupt request interval set bit 0 : every second time 1 : every forth time clock-source-of-dead-time-timer select bits 0 0 : f 2 0 1 : f 2 /2 1 0 : f 2 /4 b7 b6 interrupt validity output select bit 0 : at each even-numbered underflow of timer a3 1 : at each odd-numbered underflow of timer a3 released from w-phase output fixation. released from v-phase output fixation. released from u-phase output fixation. ? b7 b0 ? ? ? three-phase output data register 1 (address a9 16 ) ? : it may be either 0 or 1. ? ? ? b7 b0 setting of timers a0 through a2 to one-shot pulse mode timer a0/a1/a2 mode register (addresses 56 16 to 58 16 ) 1 11 0 0 count source select bits (see table 7.2.3.) setting of timer a3 to timer mode timer a3 mode register (address 59 16 ) b7 b0 0 0 0 0 0 0 0 b7 b0 setting of timer a0/a1/a2/a3 interrupt request to disabled timer a0/a1/a2/a3 interrupt control register (addresses 75 16 to 78 16 ) 0 0 0 0 no interrupt request interrupt disabled setting of timer a3 carrier wave s period b7 b0 a value in the range from 0000 16 to ffff 16 is set. b7 (b8) (b15) b0 setting of output width of each phase of timers a0 through a2 b7 b0 a value in the range from 0000 16 to ffff 16 is set. b7 (b8) (b15) b0 timer a3 register (addresses 4d 16 , 4c 16 ) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a0 1 register (addresses d1 16 , d0 16 ) timer a1 1 register (addresses d3 16 , d2 16 ) timer a2 1 register (addresses d5 16 , d4 16 ) internal output for stabilization of output level b7 b0 count start register 0 (address 40 16 ) 1 starts counting in timer a0. starts counting in timer a1. starts counting in timer a2. starts counting in timer a3. 111 ? ? count source select bits (see table 7.2.3.) 00 0
three-phase waveform mode 7906 group user s manual rev.2.0 10-28 10.4 three-phase mode 1 fig. 10.4.2 initial setting example for registers relevant to three-phase mode 1 (2) three-phase waveform output starts. continued from the preceding page. b7 b0 setting of timer a3 interrupt priority level 0 no interrupt request timer a3 interrupt control register (address 78 16 ) timer a3 interrupt priority level set to one of levels 1 through 7. check whether the timer ai interrupt request bit is 1 or not. (note that the first one-shot pulse width of timer ai must be the maximum among those of timers a0 through a2.) ? the output level is stabilized. b7 b0 three-phase waveform output is enabled. waveform output mode register (address a6 16 ) 1 three-phase waveform output is enabled. waiting for the dead time, which was previously set, to elapse
three-phase waveform mode 7906 group user s manual rev.2.0 10-29 10.4 three-phase mode 1 fig. 10.4.3 data-updating example in three-phase mode 1 timer a3 interrupt timer a0/a1/a2 data calculation for the next time interrupt processing is completed. setting of output width of each phase of timers a0 through a2 b7 b0 a value in the range from 0000 16 to ffff 16 is set. b7 (b8) (b15) b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a0 1 register (addresses d1 16 , d0 16 ) timer a1 1 register (addresses d3 16 , d2 16 ) timer a2 1 register (addresses d5 16 , d4 16 )
three-phase waveform mode 7906 group user s manual rev.2.0 10-30 10.4 three-phase mode 1 10.4.2 operation in three-phase mode 1 figure 10.4.4 shows a triangular wave modulation output example (three-phase mode 1). ? when an underflow occurs in the timer a3 counter, a timer a3 interrupt request is generated; simultaneously, the one-shot pulse outputs of timers a0 through a2 are started. also, the contents of the three-phase output polarity set buffer are transferred to the output polarity set toggle flip-flop, and then, the contents of the three-phase output polarity set buffer are reversed. ? the contents of the output polarity set toggle flip-flop are reversed at each falling edge of the one- shot pulse output of timer a0/a1/a2. simultaneously, the one-shot pulse of the dead-time timer is output. ? each of the positive and negative waveform outputs is not allowed to become l level from h level until the reversed signal of the one-shot pulse output of the dead-time timer rises. repeat procedures from ? through ? for the three-phase waveform output control. in the case of three-phase mode 1, the value of timer ai ( i = 0 through 2) and the value of timer ai 1 are counted alternately. immediately after the count start in timer ai, however, the value of the timer ai register is counted twice in succession. (it is a limitation to the case immediately after the count start in timer ai.) at this time, the timer ai s one-shot pulse becomes the same length twice in succession, also. figure 10.4.5 shows an output example at start of three-phase mode 1. for the triangular wave modulation output model (for one period), see figure 10.3.6.
three-phase waveform mode 7906 group user s manual rev.2.0 10-31 fig. 10.4.4 triangular wave modulation output example (three-phase mode 1) 10.4 three-phase mode 1 carrier wave timer a3 interrupt request timer a3 underflow signal ? 2 contents of timer a0/a1/a2 register one-shot pulse output of timer a0/a1/a2 ? 2 contents of three-phase output polarity set buffer contents of output polarity set toggle flip-flop ? 2 reversed signal of pulse output of dead-time timer ? 2 positive waveform output negative waveform output n 1 n 3 n 5 n 7 ? 1 ? 1 ? 1 ? 1 1/f i ? n 1 1/f i ? n 3 1/f i ? n 7 trans- ferred trans- ferred trans- ferred rever- sed rever- sed ? 1 : written by software ? 2 : this is an internal signal, which cannot be read from the external. f i : count source of timer a0/a1/a2 this applies under the following conditions: timer a3 interrupt request: every second time timer a3 interrupt validity output: even-numbered underflow in time a3 contents of timer a0 1 /a1 1 /a2 1 register n 2 n 4 n 6 n 8 n 9 n 10 1/f i ? n 2 1/f i ? n 6 transferred rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed 1/f i ? n 4 1/f i ? n 5 ??? ? 1 ? 1 ? 1 ? 1 rever- sed transferred transferred transferred
three-phase waveform mode 7906 group user s manual rev.2.0 10-32 10.4 three-phase mode 1 fig. 10.4.5 output example at start of three-phase mode 1 timer a0/a1/a2/a3 count start bit timer a3 interrupt request timer a3 underflow signal ? 2 contents of timer a0/a1/a2 register one-shot pulse output of timer a0/a1/a2 ? 2 contents of three-phase output polarity set buffer contents of output polarity set toggle flip-flop ? 2 reversed signal of pulse output of dead-time timer ? 2 positive waveform output negative waveform output n 3 n 5 ? 1 ? 1 ? 1 1/f i ? n 1 1/f i ? n 3 trans- ferred trans- ferred rever- sed ? 1 : written by software ? 2 : this is an internal signal, which cannot be read from the external. f i : count source of timer a0/a1/a2 this applies under the following conditions: timer a3 interrupt request: every second time timer a3 interrupt validity output: even-numbered underflow in time a3 contents of timer a0 1 /a1 1 /a2 1 register n 4 n 6 1/f i ? n 2 transferred reversed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed 1/f i ? n 4 1/f i ? n 5 ? 1 ? 1 ? 1 rever- sed undefined undefined undefined carrier wave 1/f i ? n 1 n 1 n 2 transferred transferred reversed transferred
three-phase waveform mode 7906 group user? manual rev.2.0 10-33 10.5 three-phase waveform output fixation 10.5 three-phase waveform output fixation in the three-phase waveform output, by setting of the u/v/w-phase output fix bit (bits 2 through 0 at address a8 16 ) to ?,?the output level of each phase can be fixed. the output level to be fixed (positive phase) is set by the u/v/w-phase fixed output? polarity set bit (bits 2 through 0 at address a9 16 ); in the case of the negative phase, the output level is fixed to the reversed level. the u/v/w-phase output fix bit serves synchronously with a timer a3 interrupt request. while the fixed level is output, be sure not to change the value of the u/v/w-phase fixed output? polarity set bit (bits 2 through 0 at address a9 16 ). figure 10.5.1 shows a triangular wave modulation output example using the u/v/w-phase output fix bit (three-phase mode 1). ? by software, set the following bits: ?the u/v/w-phase output fix bit (bits 2 through 0 at address a8 16 ) ?the u/v/w-phase fixed output? polarity set bit (bits 2 through 0 at address a9 16 ) ? the contents of the above bits become valid synchronously with the next timer a3 interrupt request, and then, the output level of the positive waveform is fixed to the level which was set by the u/v/w-phase fixed output? polarity set bit. in the case of the negative phase, the output level is fixed to the reversed level. ? each of the positive and negative waveform outputs is not allowed to become ??level from ??level until the reversed signal of the one-shot pulse output of the dead-time timer rises. ? the output fixation is also terminated synchronous with a timer a3 interrupt request.
three-phase waveform mode 7906 group user? manual rev.2.0 10-34 10.5 three-phase waveform output fixation fig. 10.5.1 triangular wave modulation output example using u/v/w-phase output fix bit (three-phase mode 1) ? rever- sed rever- sed carrier wave timer a3 interrupt request timer a3 underflow signal ? 2 contents of timer a0/a1/a2 register one-shot pulse output of timer a0/a1/a2 ? 2 contents of three-phase output polarity set buffer contents of output polarity set toggle flip-flop ? 2 reversed signal of pulse output of dead-time timer ? 2 positive waveform output negative waveform output n 1 n 3 n 5 n 7 ? 1 ? 1 ? 1 ? 1 1/f i ? n 1 1/f i ? n 3 1/f i ? n 7 trans- ferred trans- ferred rever- sed rever- sed ? 1 : written by software ? 2 : this is an internal signal, which cannot be read from the external. f i : count source of timer a0/a1/a2 this applies under the following conditions: timer a3 interrupt request: every second time timer a3 interrupt validity output: every even-numbered underflow in time a3 contents of timer a0 1 /a1 1 /a2 1 register n 2 n 4 n 6 n 8 n 9 n 10 1/f i ? n 2 1/f i ? n 6 transferred rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed rever- sed 1/f i ? n 4 1/f i ? n 5 ? ?? u/v/w-phase output fix bit u/v/w-phase fixed output s polarity set bit ? 1 ? 1 ? 1 trans- ferred trans- ferred ? 1 ? 1 ? 1 ? 1 rever- sed transferred rever- sed transferred
three-phase waveform mode 7906 group user s manual rev.2.0 10-35 10.6 position-data-retain function this function is used to retain the position data synchronously with the three-phase waveform output; and there are three position-data input pins for the u, v, and w phases. a trigger to retain the position data (hereafter, this trigger is referred to as retain trigger. ) can be selected by the retain-trigger polarity select bit (bit 3 at address aa 16 ); this bits selects the falling edge of each positive phase or rising edge of one. 10.6.1 operation of position-data-retain function figure 10.6.1 shows a usage example of the position-data-retain function (u phase) when a retain trigger is the falling edge of the positive signal. ? at the falling edge of the u-phase waveform output, the state at pin idu is transferred to the u-phase position data retain bit (bit 2 at address aa 16 ). ? until the next falling edge of the u-phase waveform output, the above value is retained. fig. 10.6.1 usage example of position-data-retain function (u phase) 10.6 position-data-retain function carrier wave pin idu transferred transferred u-phase position data retain bit (bit 2 at address aa 16 ) transferred transferred ? ? u-phase waveform output u-phase waveform output note: the retain trigger is the falling edge of the positive signal.
three-phase waveform mode 7906 group user s manual rev.2.0 10-36 [precautions for three-phase waveform mode] 1. when using the three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 to 0 at address a6 16 ) to 100 2 , and then, set the relevant registers. when not using the pulse output port mode and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through 0 at address a6 16 ) to 000 2 . 2. when not inactivating the three-phase waveform output by using a falling edge input to pin p6out cut , be sure to connect pin p6out cut to vcc via a resistor. 3. while the fixed level is output, be sure not to change the value of the u/v/w-phase fixed output s polarity set bit (bits 2 through 0 at address a9 16 ). [precautions for three-phase waveform mode]
chapter 11 serial i/o 11.1 overview 11.2 block description 11.3 clock synchronous serial i/o mode [precautions for clock synchronous serial i/o mode] 11.4 clock asynchronous serial i/o (uart) mode [precautions for clock asynchronous serial i/o (uart) mode]
serial i/o 7906 group user? manual rev.2.0 11-2 clock synchronous serial i/o mode transfer data length of 8 bits (lsb first) transfer data length of 8 bits (msb first) uart mode transfer data length of 7 bits transfer data length of 8 bits transfer data length of 9 bits 11.1 overview serial i/o consists of 2 channels: uart0 and uart1. they each have a transfer clock generating timer for the exclusive use of them and can operate independently. uarti (i = 0 and 1) has the following 2 operating modes: (1) clock synchronous serial i/o mode transmitter and receiver use the same clock as the transfer clock. transfer data has a length of 8 bits. (2) clock asynchronous serial i/o (uart) mode transfer rate and transfer data format can arbitrarily be set. the user can select one transfer data length from the following: 7 bits, 8 bits, and 9 bits. figure 11.1.1 shows the transfer data formats in each operating mode. 11.1 overview fig. 11.1.1 transfer data formats in each operating mode
serial i/o 7906 group user? manual rev.2.0 11-3 11.2 block description figure 11.2.1 shows the block diagram of serial i/o. registers relevant to serial i/o are described below. 11.2 block description aa aa aa aa aa aa rxd i data bus (odd) data bus (even) uarti receive register uarti receive buffer register uarti transmit buffer register receive control circuit transmit control circuit 1 / (n+1) 1/16 1/16 1/2 brgi clock synchronous (internal clock selected) uart clock synchronous uart clock synchronous (internal clock selected) clock synchronous (external clock selected) data bus (odd) data bus (even) txd i transfer clock transfer clock brg count source select bits aa aa aa aa aa uarti transmit register bit converter bit converter n: values set in uarti baud rate register (brgi) clock synchronous d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 f 2 f 16 f 64 f 512 d 8 0000000 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cts i /rts i cts i /clk i cts i clk i fig. 11.2.1 block diagram of serial i/o
serial i/o 7906 group user s manual rev.2.0 11-4 11.2.1 uarti transmit/receive mode register figure 11.2.2 shows the structure of uarti transmit/receive mode register. 11.2 block description fig. 11.2.2 structure of uarti transmit/receive mode register 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) serial i/o mode select bits internal/external clock select bit stop bit length select bit (valid in uart mode) (note) odd/even parity select bit (valid in uart mode when parity enable bit = 1. ) (note) parity enable bit (valid in uart mode) (note) sleep select bit (valid in uart mode) (note) rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 note: bits 4 to 6 are invalid in the clock synchronous serial i/o mode. (they may be either 0 or 1. ) additionally, fix bit 7 to 0. 0 0 0 : serial i/o is invalid. (p1 functions as a programmable i/o port.) 0 0 1 : clock synchronous serial i/o mode 0 1 0 : 0 1 1 : 1 0 0 : uart mode (transfer data length = 7 bits) 1 0 1 : uart mode (transfer data length = 8 bits) 1 1 0 : uart mode (transfer data length = 9 bits) 1 1 1 : do not select. b2 b1 b0 0 : internal clock 1 : external clock 0 : one stop bit 1 : two stop bits 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : sleep mode terminated (invalid) 1 : sleep mode selected do not select. bit name bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-5 (1) serial i/o mode select bits (bits 0 to 2) these bits select a uarti s operating mode. (2) internal/external clock select bit (bit 3) clock synchronous serial i/o mode by clearing this bit to 0 in order to select an internal clock, the clock which is selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the count source of the brgi. (refer to section ?1.2.6 uarti baud rate register (brgi). ) the brgi s output divided by 2 becomes the transfer clock. additionally, the transfer clock is output from the clk i pin. by setting this bit to 1 in order to select an external clock, the clock input to the clk i pin becomes the transfer clock. uart mode by clearing this bit to 0 in order to select an internal clock, the clock which is selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the count source of the brgi. (refer to section ?1.2.6 uarti baud rate register (brgi). ) then, the clk i pin functions as a programmable i/o port pin. by setting this bit to 1 in order to select an external clock, the clock input to the clk i pin becomes the count source of brgi. always in the uart mode, the brgi s output divided by 16 becomes the transfer clock. (3) stop bit length select bit, odd/even parity select bit, parity enable bit (bits 4 to 6) refer to section ?1.4.2 transfer data format. (4) sleep select bit (bit 7) refer to section ?1.4.8 sleep mode. 11.2 block description
serial i/o 7906 group user s manual rev.2.0 11-6 11.2 block description 11.2.2 uarti transmit/receive control register 0 figure 11.2.3 shows the structure of uarti transmit/receive control register 0. fig. 11.2.3 structure of uarti transmit/receive control register 0 uart0 transmit/receive control register (address 34 16 ) uart1 transmit/receive control register (address 3c 16 ) 0 1 2 3 4 5 6 7 brg count source select bits cts/rts function select bit (note 1) transmit register empty flag cts/rts enable bit uarti receive interrupt mode select bit clk polarity select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) transfer format select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : clock f 2 0 1 : clock f 16 1 0 : clock f 64 1 1 : clock f 512 0 : the cts function is selected. 1 : the rts function is selected. 0 : data is present in the transmit register. (transmission is in progress.) 1 : no data is present in the transmit register. (transmission is completed.) 0 : the cts/rts function is enabled. 1 : the cts/rts function is disabled. 0 : reception interrupt 1 : reception error interrupt 0 : at the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer clock, receive data is input. when not in transferring, pin clki s level is h. 1 : at the falling edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. when not in transferring, pin clki s level is l. 0 : lsb (least significant bit) first 1 : msb (most significant bit) first b1 b0 notes 1: valid when the cts/rts enable bit (bit 4) is 0 and cts i /rts i separate select bit (bit 0 or 1 at address ac 16 ) is 0. 2: fix these bits to 0 in the uart mode or when serial i/o is disabled. 0 0 0 1 0 0 0 0 rw rw rw ro rw rw rw rw bit name bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-7 (1) brg count source select bits (bits 0 and 1) refer to section ?1.2.1 (2) internal/external clock select bit. (2) ____ ____ cts/rts function select bit (bit 2) ____ ____ refer to section ?1.2.10 cts/rts function. (3) transmit register empty flag (bit 3) this flag is cleared to 0 when the uarti transmit buffer register s contents have been transferred to the uarti transmit register. when transmission has been completed and the uarti transmit register becomes empty, this flag is set to 1. (4) ____ ____ cts/rts enable bit (bit 4) ____ ____ refer to section ?1.2.10 cts/rts function. (5) uarti receive interrupt mode select bit (bit 5) refer to section ?1.2.7 (2) interrupt request bit. (6) clk polarity select bit (bit 6) refer to section ?1.3.1 (3) polarity of transfer clock. (7) transfer format select bit (bit 7) refer to section ?1.3.2 transfer data format. 11.2 block description
serial i/o 7906 group user s manual rev.2.0 11-8 11.2 block description 11.2.3 uarti transmit/receive control register 1 figure 11.2.4 shows the structure of uarti transmit/receive control register 1. fig. 11.2.4 structure of uarti transmit/receive control register 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) 0 1 2 3 4 5 6 7 transmit enable bit transmit buffer empty flag receive enable bit receive complete flag overrun error flag framing error flag (note) (valid in uart mode) parity error flag (note) (valid in uart mode) error sum flag (note) (valid in uart mode) b7 b6 b5 b4 b3 b2 b1 b0 0 : reception disabled 1 : reception enabled 0 : no data is present in the receive buffer register 1 : data is present in the receive buffer register note: bits 5 to 7 are invalid in the clock synchronous serial i/o mode. 0 : transmission disabled 1 : transmission enabled 0 : data is present in the transmit buffer register 1 : no data is present in the transmit buffer register 0 : no parity error 1 : parity error detected 0 : no error 1 : error detected 0 : no overrun error 1 : overrun error detected 0 : no framing error 1 : framing error detected 0 1 0 0 0 0 0 0 rw ro rw ro ro ro ro ro bit name bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-9 (1) transmit enable bit (bit 0) by setting this bit to 1, uarti enters the transmission-enabled state. by clearing this bit to 0 during transmission, uarti enters the transmission-disabled state after the transmission which was in progress at that time is completed. (2) transmit buffer empty flag (bit 1) this flag is set to 1 when data set in the uarti transmit buffer register has been transferred from the uarti transmit buffer register to the uarti transmit register. this flag is cleared to 0 when data has been set in the uarti transmit buffer register. (3) receive enable bit (bit 2) by setting this bit to 1, uarti enters the reception-enabled state. by clearing this bit to 0 during reception, uarti quits the reception immediately and enters the reception-disabled state. (4) receive complete flag (bit 3) this flag is set to 1 when data has been ready in the uarti receive register and that has been transferred to the uarti receive buffer register (i.e., when reception is completed). this flag is cleared to 0 in one of the following cases: when the low-order byte of the uarti receive buffer register has been read out when the receive enable bit (bit 2) has been cleared to 0 (5) overrun error flag (bit 4) refer to section ?1.3.7 processing on detecting overrun error and ?1.4.7 processing on detecting error. (6) framing error flag, parity error flag, error sum flag (bits 5 to 7) refer to section ?1.4.7 processing on detecting error. 11.2 block description
serial i/o 7906 group user s manual rev.2.0 11-10 11.2.4 uarti transmit register and uarti transmit buffer register figure 11.2.5 shows the block diagram for the transmitter; figure 11.2.6 shows the structure of uarti transmit buffer register. 11.2 block description fig. 11.2.5 block diagram for transmitter sp sp par 0 2sp 1sp uart 8-bit uart 7-bit uart 9-bit uart clock sync. clock sync. data bus (even) data bus (odd) txd i uarti transmit register parity enabled parity disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit uarti transmit buffer register 8-bit uart 9-bit uart aaa aaa aaa 7-bit uart clock sync. fig. 11.2.6 structure of uarti transmit buffer register uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) 8 to 0 15 to 9 b0 note: use the movm (movmb) or sta (stab, stad) instruction for writing to this register. b7 b0 b7 (b15) (b8) transmit data is set. nothing is assigned. undefined undefined wo bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-11 transmit data is set into the uarti transmit buffer register. set the transmit data into the low-order byte of this register when the microcomputer operates in the clock synchronous serial i/o mode or when a 7- bit or 8-bit length of transfer data is selected in the uart mode. when a 9-bit length of transfer data is selected in the uart mode, set the transmit data into the uarti transmit buffer register as follows: bit 8 of the transmit data into bit 0 of high-order byte of this register. bits 7 to 0 of the transmit data into the low-order byte of this register. the transmit data which has been set in the uarti transmit buffer register is transferred to the uarti transmit register when the transmission conditions are satisfied, and then it is output from the txdi pin synchronously with the transfer clock. the uarti transmit buffer register becomes empty when the data set in the uarti transmit buffer register has been transferred to the uarti transmit register. accordingly, the user can set the next transmit data. when the msb first is selected in the clock synchronous serial i/o mode, bit position of set data is reversed, and then the data of which bit position was reversed will be written, as a transmit data, into the uarti transmit buffer register. (refer to section 11.3.2 transfer data format. ) transmit operation itself is the same whichever format is selected, lsb first or msb first. when quitting the transmission which is in progress and setting the uarti transmit buffer register again, follow the procedure described bellow: ? clear the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) to 000 2 (serial i/o disabled). ? set the serial i/o mode select bits again. ? set the transmit enable bit (bit 0 at addresses 35 16 , 3d 16 ) to 1 (transmission enabled) and set transmit data in the uarti transmit buffer register. 11.2 block description
serial i/o 7906 group user s manual rev.2.0 11-12 11.2.5 uarti receive register and uarti receive buffer register figure 11.2.7 shows the block diagram of the receiver; figure 11.2.8 shows the structure of uarti receive buffer register. 11.2 block description fig. 11.2.7 block diagram of receiver aa aa a a a a clock sync. sp sp par 2sp 1sp uart 0 0 0 0 0 0 0 rxd i d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit 8-bit uart 9-bit uart 7-bit uart 9-bit uart clock sync. clock sync. 7-bit uart 8-bit uart data bus (even) data bus (odd) uarti receive register parity enabled parity disabled uarti receive buffer register aa aa aa aa fig. 11.2.8 structure of uarti receive buffer register uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) 8 to 0 15 to 9 b0 b7 b0 b7 (b15) (b8) receive data is read out from here. the value is 0 at reading. undefined 0 ro bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-13 the uarti receive register is used to convert serial data, which is input to the rxd i pin, into parallel data. this register takes in the signal input to the rxd i pin, bit by bit, synchronously with the transfer clock. the uarti receive buffer register is used to read out receive data. when reception has been completed, the receive data taken in the uarti receive register is automatically transferred to the uarti receive buffer register. note that the contents of the uarti receive buffer register is updated when the next data has been ready in the uarti receive register before the data transferred to the uarti receive buffer register is read out. (i.e., an overrun error occurs.) when msb first is selected in the clock synchronous serial i/o mode, bit position of data in the uarti receive buffer register is reversed, and then the data of which bit position was reversed will be read out as receive data. (refer to section 11.3.2 transfer data format. ) receive operation itself is the same whichever format is selected, lsb first or msb first. the uarti receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) to 1 after clearing it to 0. figure 11.2.9 shows the contents of the uarti receive buffer register at reception completed. 11.2 block description b7 b0 b7 b0 0 000000 0 000000 0 000000 receive data (9 bits) receive data (8 bits) receive data (7 bits) uart mode (transfer data length : 9 bits) clock synchronous serial i/o mode, uart mode (transfer data length : 8 bits) uart mode (transfer data length : 7 bits) same value as bit 7 in low-order byte same value as bit 6 in low-order byte high-order byte (addresses 37 16 , 3f 16 ) low-order byte (addresses 36 16 , 3e 16 ) fig. 11.2.9 contents of uarti receive buffer register at reception completed
serial i/o 7906 group user s manual rev.2.0 11-14 11.2.6 uarti baud rate register (brgi) the uarti baud rate register (brgi) is an 8-bit timer exclusively used for uarti to generate a transfer clock. it has a reload register. assuming that the value set in the brgi is n (n = 00 16 to ff 16 ), the brgi divides the count source frequency by (n + 1). in the clock synchronous serial i/o mode, the brgi is valid when an internal clock is selected, and the brgi s output divided by 2 becomes the transfer clock. in the uart mode, the brgi is always valid, and the brgi s output divided by 16 becomes the transfer clock. the data written to the brgi is written to both the timer and the reload register whichever transmission/ reception is in progress or not. accordingly, writing to these register must be performed while transmission/ reception halts. figure 11.2.10 shows the structure of the uarti baud rate register (brgi); figure 11.2.11 shows the block diagram of transfer clock generating section. 11.2 block description brgi 1/2 transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation brgi 1/16 f i : clock selected by brg count source select bits (f 2 , f 16 , f 64 , or f 512 ) f ext : clock input to clk i pin (external clock) 1/16 f i f ext f ext f i fig. 11.2.11 block diagram of transfer clock generating section fig. 11.2.10 structure of uarti baud rate register (brgi) undefined 7 to 0 uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) any value in the range from 00 16 to ff 16 can be set. assuming that the set value = n, brgi divides the count source frequency by (n + 1). wo b0 note: writing to this register must be performed while the transmission/reception halts. use the movm (movmb) or sta (stab, stad) instruction for writing to this register. b7 bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-15 11.2.7 uarti transmit interrupt control and uarti receive interrupt control registers when using uarti, 2 types of interrupts (uarti transmit and uarti receive interrupts) can be used. each interrupt has its corresponding interrupt control register. figure 11.2.12 shows the structure of uarti transmit interrupt control and uarti receive interrupt control registers. for details about these interrupts, refer to chapter 6. interrupts. for the uarti receive interrupt, a receive or receive error interrupt can be selected by the uarti receive interrupt mode selected bit (bit 5 at addresses 34 16 , 3c 16 ). 11.2 block description fig. 11.2.12 structure of uarti transmit interrupt control and uarti receive interrupt control registers uart0 transmit interrupt control register (address 71 16 ) uart0 receive interrupt control register (address 72 16 ) uart1 transmit interrupt control register (address 73 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 7 to 4 interrupt priority level select bits interrupt request bit nothing is assigned. note: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 0 0 0 undefined rw rw rw rw (note) bit name bit function at reset r/w
serial i/o 7906 group user s manual rev.2.0 11-16 11.2 block description (1) interrupt priority level select bits (bits 0 to 2) these bits select a priority level of the uarti transmit interrupt or uarti receive interrupt. when using uarti transmit/receive interrupts, select one of the priority levels (1 to 7). when a uarti transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0. ) to disable uarti transmit/ receive interrupts, be sure to set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) the uarti transmit interrupt request bit is set to 1 when data has been transferred from the uarti transmit buffer register to the uarti transmit register. the uarti receive interrupt request bit functions as below: when receive interrupt is selected (bit 5 = 0 at addresses 34 16 , 3c 16 ) the uarti receive interrupt request bit is set to 1 when data has been transferred from the uarti receive register to the uarti receive buffer register. (however, the uarti receive interrupt request bit does not change when an overrun error has occurred.) when receive error interrupt is selected (bit 5 = 1 at addresses 34 16 , 3c 16 ) the uarti receive interrupt request bit is set to 1 when an error (an overrun error in the clock synchronous serial i/o mode; an overrun error, framing error, or parity error in uart mode) has occurred. each interrupt request bit is automatically cleared to 0 when its corresponding interrupt request has been accepted. this bit can be set to 1 or cleared to 0 by software.
serial i/o 7906 group user s manual rev.2.0 11-17 fig. 11.2.13 structure of serial i/o pin control register (1) cts 0 /rts 0 separate select bit (bit 0) refer to section 11.2.10 cts/rts function. (2) cts 1 /rts 1 separate select bit (bit 1) refer to section 11.2.10 cts/rts function. (3) txd 0 /p1 3 switch bit (bit 2) when this bit is set to 1, the txd 0 pin functions as a programmable i/o port pin (p1 3 ). when only reception is performed, the txd 0 pin can be used as the p1 3 pin. when performing transmission, be sure to clear this bit to 0. (4) txd 1 /p1 7 switch bit (bit 3) when this bit is set to 1, the txd 1 pin functions as a programmable i/o port pin (p1 7 ). when only reception is performed, the txd 1 pin can be used as the p1 7 pin. when preforming transmission, be sure to clear this bit to 0. 11.2 block description 11.2.8 serial i/o pin control register figure 11.2.13 shows the structure of the seral i/o pin control register. serial i/o pin control register (address ac 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 7 to 4 cts 0 /rts 0 separate select bit (note) cts 1 /rts 1 separate select bit (note) txd 0 /p1 3 switch bit txd 1 /p1 7 switch bit the value is 0 at reading. 0 : cts 0 /rts 0 are used together. 1 : cts 0 /rts 0 are separated. 0 : functions as txd 1 . 1 : functions as p1 7 . rw rw rw rw bit name bit function at reset r/w 0 : cts 1 /rts 1 are used together. 1 : cts 1 /rts 1 are separated. 0 : functions as txd 0 . 1 : functions as p1 3 . 0 0 0 0 0 note: valid when the cts/rts enable bit (bit 4 at addresses 34 16 and 3c 16 ) is 0.
serial i/o 7906 group user s manual rev.2.0 11-18 11.2 block description 11.2.9 port p8 direction register i/o pins for serial i/o are multiplexed with port p1 pins. when using pins p1 1 , p1 2 , p1 5 , and p1 6 as serial i/o s input pins (cts i , rxd i ), clear the corresponding bits of the port p1 direction register to 0 in order to set these pins for the input mode. when using these pins as other serial i/o s pins (cts i /rts i , clk i , txd i ), these pins are forcibly set as i/o pins for serial i/o regardless of the port p8 direction register s contents. figure 11.2.14 shows the relationship between the port p1 direction register and serial i/o s i/o pins. for details, refer to the description of each operating mode. fig. 11.2.14 relationship between port p1 direction register and serial i/o s i/o pins corresponding pin name bit 0 1 2 3 4 5 6 7 port p1 direction register (address 5 16 ) function at reset r/w pin cts 0 /rts 0 pin cts 0 /clk 0 pin rxd 0 pin txd 0 pin cts 1 /rts 1 pin cts 1 /clk 1 pin rxd 1 pin txd 1 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode 1 : output mode when using pins p1 1 , p1 2 , p1 5 , and p1 6 as serial i/o s input pins (cts 0 , rxd 0 , cts 1 , rxd 1 ), clear the corresponding bits to 0.
serial i/o 7906 group user s manual rev.2.0 11-19 11.2.10 cts/rts function when the cts function is selected, the signal input to the cts i pin must be at l level. (this is one of the transmit conditions.) when the rts function is selected, the rts i pin outputs the following signals: (1) clock synchronous serial i/o mode when the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) = 0 (reception disabled), the rts i pin outputs h level. when the receive enable bit = 0 (reception disabled), the rts i pin outputs l level by setting the receive enable bit to 1, or by reading the low-order byte of the uarti receive buffer register. when the receive enable bit = 1 (continuously reception), the rts i pin outputs l level by reading the low-order byte of the uarti receive buffer register. when reception has started, the rts i pin outputs h level. when an internal clock is selected (bit 3 at addresses 30 16 , 38 16 = 0 ), do not select the rts function because the rts output is undefined. (2) uart mode when the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) = 0 (reception disabled), the rts i pin outputs h level. when the receive enable bit = 0 (reception disabled), the rts i pin outputs l level by setting the receive enable bit to 1, or by reading the low-order byte of the uarti receive buffer register. when the receive enable bit = 1 (continuously reception), the rts i pin outputs l level by reading the low-order byte of the uarti receive buffer register. when reception has started, the rts i pin outputs h level. selection of the cts/rts function depends on the following bits. cts/rts function select bit (bit 2 at addresses 34 16 , 3c 16 : see figure 11.2.3.) cts/rts enable bit (bit 4 at addresses 34 16 , 3c 16 : see figure 11.2.3.) cts 0 /rts 0 separate select bit (bit 0 at address ac 16 : see figure 11.2.13.) cts 1 /rts 1 separate select bit (bit 1 at address ac 16 : see figure 11.2.13.) table 11.2.1 lists the selection of the cts/rts function. 11.2 block description ? : it may be either 0 or 1. notes 1: when using the p1 1 or p1 5 pin as the cts i pin, be sure to clear the corresponding bit of the port p1 direction register to 0. 2: when cts i /rts i separation is selected, the clk i pin cannot be used. accordingly, cts i /rts i cannot be separated in the clock synchronous serial i/o mode. when separating cts i /rts i in uart mode, be sure to select an internal clock. table 11.2.1 selection of cts/rts function 0 1 ? ? 0 1 ? cts/rts enable bit functions 0 1 cts i /rts i separate select bit cts/rts function select bit p1 0 /cts 0 /rts 0 pin cts 0 rts 0 rts 0 p1 0 p1 1 or clk 0 p1 1 or clk 0 cts 0 (notes 1, 2) p1 1 or clk 0 p1 1 /cts 0 /clk 0 pin p1 4 /cts 1 /rts 1 pin cts 1 rts 1 rts 1 p1 4 p1 5 or clk 1 p1 5 or clk 1 cts 1 (notes 1, 2) p1 5 or clk 1 p1 5 /cts 1 /clk 1 pin
serial i/o 7906 group user? manual rev.2.0 11-20 11.3 clock synchronous serial i/o mode 11.3 clock synchronous serial i/o mode table 11.3.1 lists the performance overview in the clock synchronous serial i/o mode, and table 11.3.2 lists the functions of i/o pins in this mode. table 11.3.1 performance overview in clock synchronous serial i/o mode item transfer data format transfer rate transmit/receive control when selecting internal clock when selecting external clock functions transfer data has a length of 8 bits. lsb first or msb first can be selected by software. brgi? output divided by 2 maximum 5 mbps cts function or rts function can be selected by software. table 11.3.2 functions of i/o pins in clock synchronous serial i/o mode functions serial data output pin programmable i/o port pin serial data input pin programmable i/o port pin transfer clock output pin transfer clock input pin cts input pin rts output pin programmable i/o port pin name txd i (p1 3 , p1 7 ) rxd i (p1 2 , p1 6 ) clk i (p1 1 , p1 5 ) cts i , rts i (p1 0 , p1 1 , p1 4 , p1 5 ) method of selection txd 0 /p1 3 or txd 1 /p1 7 switch bit = ? (dummy data is output when performing only reception.) (note) txd 0 /p1 3 or txd 1 /p1 7 switch bit = ? port p1 direction register? corresponding bit = ? ?(can be used as an i/o port pin when performing only transmission.) internal/external clock select bit = ? internal/external clock select bit = ? see table 11.2.1. port p1 direction register: address 05 16 internal/external clock select bit: bit 3 at addresses 30 16 , 38 16 txd 0 /p1 3 switch bit: bit 2 at address ac 16 txd 1 /p1 7 switch bit: bit 3 at address ac 16 note: the txd i pin outputs ??level until transmission starts after uarti? operating mode is selected. 11.3.1 transfer clock (synchronizing clock) data transfer is performed synchronously with a transfer clock. for the transfer clock, the following selection is possible: whether to generate a transfer clock internally or to input it from the external. polarity of transfer clock. the transfer clock is generated by operation of the transmit control circuit. accordingly, even when performing only reception, set the transmit enable bit to ?,?and set dummy data in the uarti transmit buffer register in order to make the transmit control circuit active. (1) internal generation of transfer clock the count source selected with the brg count source select bits is divided by the brgi, and the brgi output is further divided by 2. this divided output is the transfer clock. the transfer clock is output from the clk i pin. transfer clock? frequency = f i : frequency of brgi? count source (f 2 , f 16 , f 64 , or f 512 ) n: setting value of brgi f i 2 (n+1)
serial i/o 7906 group user? manual rev.2.0 11-21 11.3 clock synchronous serial i/o mode (2) input of transfer clock from the external a clock input from the clk i pin becomes the transfer clock. (3) porarity of transfer clock as shown in figure 11.3.1, the polarity of the transfer clock can be selected by the clk polarity select bit (bit 6 at addresses 34 16 , 3c 16 ). fig. 11.3.1 polarity of transfer clock clk polarity select bit = 0 clk i d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ? the transmit data is output to the txd i pin at the falling edge of a transfer clock, and the receive data is input from the rxd i pin at the rising edge of the transfer clock. the level at the clk i pin is h when the transfer is not performed. clk polarity select bit = 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ? the transmit data is output to the txd i pin at the rising edge of a transfer clock, and the receive data is input from the rxd i pin at the falling edge of the transfer clock. the level at the clki pin is l when the transfer is not performed. txd i rxd i clk i txd i rxd i
serial i/o 7906 group user s manual rev.2.0 11-22 11.3 clock synchronous serial i/o mode 11.3.2 transfer data format lsb first or msb first can be selected as the transfer data format. table 11.3.3 lists the relationship between the transfer data format and writing/reading to and from the uarti transmit/receive buffer register. the transfer format select bit (bit 7 at addresses 34 16 , 3c 16 ) selects the transfer data format. when this bit is cleared to 0, the set data is written to the uarti transmit buffer register as the transmit data, as it is. similarly, the data in the uarti receive buffer register is read out as the receive data, as it is. (see the upper row in table 11.3.3.) when this bit is set to 1, each bit s position of set data is reversed, and the resultant data will be written to the uarti transmit buffer register as the transmit data. similarly, each bit s position of data in the uarti receive buffer register is reversed, and the resultant data will be read out as the receive data. (see the lower row in table 11.3.3.) note that only the method of writing/reading to and from the uarti transmit/receive buffer register is affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by it. table 11.3.3 relationship between transfer data format and writing/reading to and from uarti transmit/ receive buffer register writing to uarti transmit buffer register reading from uarti receive buffer register data bus uarti transmit buffer register db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 data bus uarti receive buffer register db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 lsb (least significant bit) first data bus uarti transmit buffer register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data bus uarti receive buffer register msb (most significant bit) first transfer data format transfer format select bit 0 1 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
serial i/o 7906 group user s manual rev.2.0 11-23 11.3 clock synchronous serial i/o mode 11.3.3 method of transmission figure 11.3.2 shows an initial setting example for relevant registers when transmitting. transmission is started when all of the following conditions ( ? to ? ) has been satisfied. when an external clock is selected, satisfy conditions ? to ? with the following preconditions satisfied. the clk i pin s input is at h level (external clock selected, when the clk polarity select bit = 0 ) the clk i pin s input is at l level (external clock selected, when the clk polarity select bit = 1 ) note: when an internal clock is selected, the above preconditions are ignored. ? transmit data is present in the uarti transmit buffer register (transmit buffer empty flag = 0 ) ? transmission is enabled (transmit enable bit = 1 ). ? the cts i pin s input is at l level (when the cts function selected). note : when the cts function is not selected, condition ? is ignored. by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section ?1.3.6 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to ?hapter 6. interrupts. figure 11.3.3 shows the write operation of data after transmission start, and figure 11.3.4 shows the detect operation of transmit completion.
serial i/o 7906 group user s manual rev.2.0 11-24 11.3 clock synchronous serial i/o mode fig. 11.3.2 initial setting example for relevant registers when transmitting 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock ? ?? ? : it may be either 0 or 1. selection of clock synchronous serial i/o mode uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bit s cts / rts function select bit 0: cts function selected 1: rts function selected 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b0 transmission starts. uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 transmit data is set. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission is enabled. (in the case of selecting the cts function, transmission starts when the cts 0 pin s input level is l. ) uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. cts / rts enable bit 0: cts / rts function is enabled. 1: cts / rts function is disabled. clk polarity select bit 0: at the falling edge of the transfer clock, transmit data is output. 1: at the rising edge of the transfer clock, transmit data is output. transfer format select bit 0: lsb first 1: msb first serial i/o pin control register (address ac 16 ) b7 b0 cts 0 /rts 0 separate select bit 0: cts 0 /rts 0 are used together (note) . note: in the clock synchronous serial i/o mode, cts i /rts i separation cannot be selected. (refer to section [pre- cautions for clock synchronous serial i/o mode]. ) when extenal clock is selected when internal clock is selecte d 1 0 0 cts 1 /rts 1 separate select bit 0: cts 1 /rts 1 are used together (note) . txd 0 /p1 3 switch bit 0: functions as txd 0 . txd 1 /p1 7 switch bit 0: functions as txd 1 .
serial i/o 7906 group user s manual rev.2.0 11-25 11.3 clock synchronous serial i/o mode fig. 11.3.4 detect operation of transmit completion [when not using interrupts] [when using interrupts] uarti transmit interrupt uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b 0 interrupt request bit checking start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 checking completion of transmission transmit register empty flag 0: transmission is in progress. 1: transmission is completed. processing at completion of transmission 0: no interrupt requested 1: interrupt requested (transmission has started.) a uarti transmit interrupt request occurs when the transmission starts. note: this figure shows the bits and registers required for processing. see figures 11.3.6 and 11.3.7 for the change of flag state and the occurrence timing of an interrupt request. [when not using interrupts] [when using interrupts] a uarti transmit interrupt request occurs when the transbission starts (when the uarti transmit buffer register becomes empty). uarti transmit interrupt note: uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 writing of next transmit data transmit data is set. b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 transmit buffer empty flag 0: data is present in transmit buffer register. 1: no data is present in transmit buffer register. (writing of next transmit data is possible.) checking state of uarti transmit buffer register 1 this figure shows the bits and registers required for processing. see figures 11.3.6 and 11.3.7 for the change of flag state and the occurrence timing of an interrupt request. b0 fig. 11.3.3 write operation of data after transmission start
serial i/o 7906 group user s manual rev.2.0 11-26 11.3 clock synchronous serial i/o mode 11.3.4 transmit operation when the transmit conditions described in section 11.3.3 method of transmission have been satisfied in the case of an internal clock selected, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock or less has passed. in the case of an external clock selected, when the transmit conditions have been satisfied and then an external clock is input to the clk i pin, the following operations are automatically performed: the uarti transmit buffer register s contents are transferred to the uarti transmit register. the transmit buffer empty flag is set to 1. the transmit register empty flag is cleared to 0. 8 transfer clocks are generated (in the case of an internal clock selected). a uarti transmit interrupt request occurs, and the interrupt request bit is set to 1. the transmit operations are described below: ? data in the uarti transmit register is transmitted from the txd i pin synchronously with the valid edge ? of the clock output from or input to the clk i pin. ? this data is transmitted, bit by bit, sequentially beginning with the least significant bit. ? when 1-byte data has been transmitted, the transmit register empty flag is set to 1. this indicates the completion of transmission. valid edge ? : a falling edge is selected when the clk polarity select bit = 0. a rising edge is selected when the clk polarity select bit = 1. figure 11.3.5 shows the transmit operation. when an internal clock is selected, if the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. accordingly, when performing transmission continuously, set the next transmit data to the uarti transmit buffer register during transmission (when the transmit register empty flag = 0 ). when the transmit conditions for the next data are not satisfied, the transfer clock stops at h level (when the clk polarity select bit = 0 ), or l level (when the clk polarity select bit = 1 ). figures 11.3.6 and 11.3.7 show examples of transmit timing. fig. 11.3.5 transmit operation transfer clock output from or input to the clki pin ( note ) uarti transmit buffer register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 7 d 6 d 5 d 4 d 3 transmit data msb b7 b0 d 0 d 1 d 2 d 7 lsb uarti transmit register note: this applies when the clk polarity select bit = 0. when the clk polarity select bit = 1, data is shifted at the rising edge of the transfer clock.
serial i/o 7906 group user s manual rev.2.0 11-27 11.3 clock synchronous serial i/o mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk clk i t end i txd i transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. uarti transmit register uarti transmit buffer register. stopped because transmit enable bit = 0. t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = t clk = 2(n+1) /fi fi: brgi count source frequency n: value set in brgi cleared to 0 when interrupt request is accepted or cleared to 0 by software. the above timing diagram applies when the following conditions are satisfied: internal clock selected cts function not selected clk polarity select bit = 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc cts i clk i t end i txd i transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit t clk data is set in uarti transmit buffer register. uarti transmit register uarti transmit buffer register. stopped because cts i = h. stopped because transmit enable bit = 0. t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = t clk = 2(n+1) /fi fi: brgi count source frequency n: value set in brgi cleared to 0 when interrupt request is accepted or cleared to 0 by software. the above timing diagram applies when the following conditions are satisfied: internal clock selected cts function selected clk polarity select bit = 0 fig. 11.3.6 example of transmit timing (when internal clock and cts function selected) fig. 11.3.7 example of transmit timing (when internal clock selected and cts function not selected)
serial i/o 7906 group user s manual rev.2.0 11-28 11.3 clock synchronous serial i/o mode 11.3.5 method of reception figure 11.3.8 shows an initial setting example for relevant registers when receiving. reception is started when all of the following conditions ( ? to ? ) have been satisfied. when an external clock is selected, satisfy conditions ? to ? with the following preconditions satisfied. the clk i pin s input is at h level (external clock selected, when the clk polarity select bit = 0 ). the clk i pin s input is at l level (external clock selected, when the clk polarity select bit = 1 ). note: when an internal clock is selected, the above preconditions are ignored. ? dummy data is present in the uarti transmit buffer register (transmit buffer empty flag = 0 ) ? reception is enabled (receive enable bit = 1 ). ? transmission is enabled (transmit enable bit = 1 ). by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section 11.3.6 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to chapter 6. interrupts. figure 11.3.9 shows processing after reception is completed.
serial i/o 7906 group user s manual rev.2.0 11-29 11.3 clock synchronous serial i/o mode fig. 11.3.8 initial setting example for relevant registers when receiving 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock ? ?? ? : it may be either 0 or 1. selection of clock synchronous serial i/o mode uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bits cts/rts function select bit 0: cts function selected 1: rts function selected 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b 0 reception starts. uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 dummy data is set. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission enabled uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. cts/rts enable bit 0: cts/rts function is enabled. 1: cts/rts function is disabled . clk polarity select bit 0: at the rising edge of the transfer clock, receive data is input. 1: at the falling edge of the transfer clock, receive data is input. transfer format select bit 0: lsb first 1: msb first when extenal clock is selected uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . when internal clock is selecte d uarti receive interrupt mode select bit 0: reception interrupt 1: reception error interrupt 0 port p1 direction register (address 5 16 ) b7 b0 pin rxd 0 pin rxd 1 1 reception enable bit 1: reception enabled note: set the receive enable bit and the transmit enable bit to 1 simultaneously. 1 0 0 serial i/o pin control register (address ac 16 ) b7 b0 cts 0 /rts 0 separate select bit 0: cts 0 /rts 0 are used together (note 1) . notes 1: in the clock synchronous serial i/o mode, cts i /rts i separation cannot be selected. (refer to section [pre- cautions for clock synchronous serial i/o mode]. ) 2: when only reception is performed, if these bits = 1, the txd i pin can be used as a programmable i/o port pin. cts 1 /rts 1 separate select bit 0: cts 1 /rts 1 are used together (note 1) . txd 0 /p1 3 switch bit (note 2) 0: functions as txd 0 . 1: functions as p1 3 . txd 1 /p1 7 switch bit (note 2) 0: functions as txd 1 . 1: functions as p1 7 .
serial i/o 7906 group user s manual rev.2.0 11-30 11.3 clock synchronous serial i/o mode fig. 11.3.9 processing after reception is completed [when not using interrupts] [when using interrupts] a uarti receive interrupt request occurs when reception is completed. uarti receive interrupt processing after reading out receive data uart0 receive buffer register (address 36 16 ) uart1 receive buffer register (address 3e 16 ) b7 b0 reading of receive data ( note 2 ) read out receive data. b7 b 0 checking completion of reception 1 1 notes 1: when performing the processing after reception is completed, using an interrupt, be sure to select a receive interrupt (uarti receive interrupt mode select bit = 0. ) 2: in the case of an external clock and the rts function selected, the rts i output level becomes l when the uarti receive buffer register is read out. accordingly, when performing reception continuously, be sure to write the dummy data to the uarti transmit buffer register before reading out the uarti receive buffer register. 3: this figure shows the bits and registers required for the processing. see figure 11.3.12 for the change of flag state and the occurrence timing of an interrupt request. b7 b0 checking erro r 1 1 overrun error flag 0 : no overrun error 1 : overrun error detected uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) receive complete flag 0 : reception not completed 1 : reception completed ( note 1 )
serial i/o 7906 group user s manual rev.2.0 11-31 11.3 clock synchronous serial i/o mode 11.3.6 receive operation in the case of an internal clock selected, when the receive conditions described in section 11.3.5 method of reception have been satisfied, a transfer clock is generated and the reception is started after 1 cycle of the transfer clock or less has passed. in the case of an external clock selected, when the receive conditions have been satisfied, the uarti enters the receive-enabled state, and then reception will be started when an external clock is input to the clki pin. in the case of an external clock selected, when connecting the rts i pin to the cts i pin of the transmitter side, the timing of transmission and that of reception can be matched. in the case of an internal clock selected, do not use the rts function. it is because the rts output is undefined in the case of an internal clock selected. in the case of an external clock and the rts function selected, the rts i pin s output level becomes as described below. when the receive enable bit = 0, if one of the following is performed, the rts i pin s output level becomes l and informs of the transmitter side that reception has become enabled: the receive enable bit is set to 1. the low-order byte of the uarti receive buffer register is read out. when the receive enable bit = 1, if the low-order byte of the uarti receive buffer register is read out, the rts i pin s output level becomes l. accordingly, when performing reception continuously, an overrun occurrence can be avoided because the rts output level does not become l until the receive data is read out. when reception has started, the rts i pin s output level becomes h. figure 11.3.10 shows a connection example. fig. 11.3.10 connection example txd i rxd i clk i txd i rxd i clk i transmitter side receiver side cts i rts i
serial i/o 7906 group user s manual rev.2.0 11-32 11.3 clock synchronous serial i/o mode the receive operations are described below: ? the signal input to the rxd i pin is taken into the most significant bit of the uarti receive register synchronously with the valid edge ? of the clock output from the clk i pin or input to the clk i pin. ? the contents of the uarti receive register are shifted, bit by bit, to the right. ? steps ? and ? are repeated at each valid edge of the clock output from the clk i pin or input to the clk i pin. ? when 1-byte data has been prepared in the uarti receive register, the contents of this register are transferred to the uarti receive buffer register. ? simultaneously with step ? , the receive complete flag is set to 1. additionally, when the receive interrupt is selected (uarti receive interrupt mode select bit = 0 ), a uarti receive interrupt request occurs and its interrupt request bit is set to 1. valid edge ? : a rising edge is selected when the clk polarity select bit = 0. a falling edge is selected when the clk polarity select bit = 1. the receive complete flag is cleared to 0 when the low-order byte of the uarti receive buffer register is read out. figure 11.3.11 shows the receive operation, and figure 11.3.12 shows an example of receive timing (when an external clock is selected). when the transfer format select bit is 1 (msb first), each bit s position of this register s contents is reversed, and then the resultant data is read out.
serial i/o 7906 group user s manual rev.2.0 11-33 11.3 clock synchronous serial i/o mode fig. 11.3.11 receive operation fig. 11.3.12 example of receive timing (when external clock selected) uarti receive register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 0 receive data msb b7 b0 lsb d 2 d 1 d 0 transfer clock output from or input to clki pin ( note ). uarti receive buffer register note: this applies when the clk polarity select bit = 0. when the clk polarity select bit = 1, data is shifted at the rising edge of the transfer clock. the above timing diagram applies when the following conditions are satisfied: external clock selected rts function selected clk polarity select bit = 0 f ext : frequency of external clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 1/f ext rts i clk i rxd i when the clk i pin s input level is h, be sure to sat i the following conditions: writing of dummy data to uarti transmit buffer r e transmit enable bit = 1 receive enable bit = 1 receive enable bit transmit enable bit transmit buffer empty flag dummy data is set to uarti transmit buffer register. uarti transmit register uarti transmit buffe r receive data is taken in. uarti receive register uarti receive buffer register uarti receive buffer register is read o receive complete flag uarti receive interrupt request bit cleared to 0 when interrupt request is accepted or cleared to 0 by software.
serial i/o 7906 group user s manual rev.2.0 11-34 11.3 clock synchronous serial i/o mode 11.3.7 processing on detecting overrun error in the clock synchronous serial i/o mode, an overrun error can be detected. an overrun error occurs when the next data has been prepared in the uarti receive register with the receive complete flag = 1 (i.e. data is present in the uarti receive buffer register) and next data is transferred to the uarti receive buffer register. in other words, an overrun error occurs when the next data has been prepared before reading out the contents of the uarti receive buffer register. when an overrun error has occurred, the next receive data is written into the uarti receive buffer register. additionally, when the receive error interrupt is selected (uarti receive interrupt mode select bit = 1 ), a uarti receive interrupt request occurs and its interrupt request bit is set to 1. when the receive interrupt is selected (uarti receive interrupt mode select bit = 0 ), the uarti receive interrupt request bit does not change. an overrun error is detected when data is transferred from the uarti receive register to the uarti receive buffer register, and the overrun error flag is set to 1. the overrun error flag is cleared to 0 by clearing the receive enable bit to 0. when an overrun error occurs during reception, be sure to initialize the overrun error flag and uarti receive buffer register, and then perform reception again. when it is necessary to perform retransmission owing to a receiver-side overrun error which has occurred during transmission, be sure to set the uarti transmit buffer register again, and start transmission again. the methods of initializing the uarti receive buffer register and that of setting the uarti transmit buffer register again are described below. (1) method of initializing uarti receive buffer register ? clear the receive enable bit to 0 (reception disabled). ? set the receive enable bit to 1 again (reception enabled). (2) method of setting uarti transmit buffer register again ? clear the serial i/o mode select bits to 000 2 (serial i/o invalidated). ? set the serial i/o mode select bits to 001 2 again. ? set the transmit enable bit to 1 (transmission enabled), and set the transmit data to the uarti transmit buffer register.
serial i/o 7906 group user s manual rev.2.0 11-35 [precautions for clock synchronous serial i/o mode] [precautions for clock synchronous serial i/o mode] 1. a transfer clock is generated by operation of the transmit control circuit. accordingly, even when performing only reception, the transmit operation (in other words, setting for transmission) must be performed. in this case, be sure to set as follows. additionally, in this case, dummy data is output from the txd i pin to the external: when performing reception, be sure to enable the reception after dummy data is set to the low-order byte of the uarti transmit buffer register. also, be sure to set dummy data at each 1-byte data reception. at reception, be sure to set the receive enable bit and transmit enable bit to 1 simultaneously. when performing only reception, if any of the txd 0 /p1 3 and txd 1 /p1 7 switch bits (bits 2 and 3 at address ac 16 ) is set to 1, the corresponding txd i pin can be used as a programmable i/o port pin. 2. when an external clock is selected, with the input level at the clk i pin = h (the clk polarity select bit = 0 ) or l (the clk polarity select bit = 1 ), be sure to satisfy all of the following three conditions: ? transmit data is written to the uarti transmit buffer register. ? the transmit enable bit is set to 1. ? l level is input to the cts i pin (when the cts function selected). ? dummy data is written to the uarti transmit buffer register. ? the receive enable bit is set to 1. ? the transmit enable bit is set to 1. 3. while the cts i /rts i separation is selected, the clk i pin cannot be used. accordingly, in the clock synchronous serial i/o mode, the cts i /rts i separation cannot be selected. 4. writing to the uarti baud rate register (brgi) must be performed while transmission/reception halts. 5. when an internal clock is selected, do not use the rts function because the rts output is undefined. 6. when performing transmission, be sure to clear any of the txd 0 /p1 3 and txd 1 /p1 7 switch bits to 0 (bits 2 and 3 at address ac 16 ).
serial i/o 7906 group user? manual rev.2.0 11-36 11.4 clock asynchronous serial i/o (uart) mode 11.4 clock asynchronous serial i/o (uart) mode table 11.4.1 lists the performance overview in the uart mode, and table 11.4.2 lists the functions of i/o pins in this mode. table 11.4.1 performance overview in uart mode item transfer data format transfer rate error detection start bit character bit (transfer data) parity bit stop bit when selecting internal clock when selecting external clock functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (odd or even can be selected.) 1 bit or 2 bits brgi? output divided by 16 maximum 312.5 kbps 4 types (overrun, framing, parity, and summing): presence of an error can be detected only by check of the error sum flag. table 11.4.2 functions of i/o pins in uart mode method of selection txd 0 /p1 3 or txd 1 /p1 7 switch bit = ?.? (note) txd 0 /p1 3 or txd 1 /p1 7 switch bit = ?. port p1 direction register? corresponding bit = ? ?(can be used as a programmable i/o port pin when performing only transmission.) internal/external clock select bit = ? internal/external clock select bit = ? see table 11.2.1. pin name txd i (p1 3 , p1 7 ) rxd i (p1 2 , p1 6 ) clk i (p1 1 , p1 5 ) cts i / rts i (p1 0 , p1 1 , p1 4 , p1 5 ) functions serial data output pin programmable i/o port pin serial data input pin programmable i/o port pin brgi? count source input pin programmable i/o port pin cts input pin rts output pin programmable i/o port pin port p1 direction register: address 05 16 internal/external clock select bit: bit 3 at addresses 30 16 , 38 16 txd 0 /p1 3 switch bit: bit 2 at address ac 16 txd 1 /p1 7 switch bit: bit 3 at address ac 16 note: the txd i pin outputs ??level while transmission is not performed after the uarti? operating mode is selected.
7906 group user? manual rev.2.0 11-37 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.1 transfer rate (frequency of transfer clock) the transfer rate is determined by the brgi (addresses 31 16 , 39 16 ). when ??is set into brgi, brgi divides the count source frequency by (n + 1). the brgi? output is further divided by 16, and the resultant clock becomes the transfer clock. accordingly, ??is expressed by the following formula. n = 1 f 16 ? b n: value set in brgi (00 16 to ff 16 ) f: brgi? count source frequency (hz) b: transfer rate (bps) an internal clock or an external clock can be selected as the brgi? count source with the internal/external clock select bit (bit 3 at addresses 30 16 , 38 16 ). when an internal clock is selected, the clock selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the brgi? count source. when an external clock is selected, the clock input to the clk i pin becomes the brgi? count source. be sure to set the same transfer rate for both transmitter and receiver sides. tables 11.4.3 and 11.4.4 list the setting examples of transfer rate. each of the values, listed in these tables, realizes the actual transfer rate of which error toward an ideal transfer rate is within 1 %. table 11.4.3 setting examples of transfer rate (1) table 11.4.4 setting examples of transfer rate (2) note: this applies when the peripheral device? clock select bits 1, 0 (bits 7, 6 at address bc 16 ) = ?0 2 . brgi? set value: n (note) 63 (3f 16 ) 127 (7f 16 ) 63 (3f 16 ) 31 (1f 16 ) 127 (7f 16 ) 63 (3f 16 ) 42 (2a 16 ) 31 (1f 16 ) 15 (0f 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14288.37 19200.00 38400.00 brgi? count source f 64 f 16 f 16 f 2 f 2 f 2 f 2 brgi? set value: n (note) 64 (40 16 ) 129 (81 16 ) 64 (40 16 ) 129 (81 16 ) 64 (40 16 ) 42 (2a 16 ) 19 (13 16 ) actual time (bps) 300.48 600.96 1201.92 4807.69 9615.38 14534.88 31250.00 brgi? count source f 64 f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f sys = 20 mhz f sys = 19.6608 mhz transfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 38400 brgi? set value: n (note) 51 (33 16 ) 103 (67 16 ) 51 (33 16 ) 207 (cf 16 ) 103 (67 16 ) 51 (33 16 ) 34 (22 16 ) 25 (19 16 ) 15 (0f 16 ) 12 (0c 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14262.86 19200.00 31200.00 38400.00 brgi? count source f 64 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f 2 brgi? set value: n (note) 51 (33 16 ) 103 (67 16 ) 51 (33 16 ) 207 (cf 16 ) 103 (67 16 ) 51 (33 16 ) 25 (19 16 ) 15 (0f 16 ) 12 (0c 16 ) actual time (bps) 300.48 600.96 1201.92 2403.85 4807.69 9615.38 19230.77 31250.00 38461.51 brgi? count source f 64 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f 2 f 2 f sys = 16 mhz f sys = 15.9744 mhz transfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 38400 note: this applies when the peripheral device? clock select bits 1, 0 (bits 7, 6 at address bc 16 ) = ?0 2 .
serial i/o 7906 group user? manual rev.2.0 11-38 11.4 clock asynchronous serial i/o (uart) mode error-permitted range of transfer baud during reception, the receive data input to the rxd i pin is taken at the rising edge of the transfer clock. (refer to section ?1.4.6 receive operation. ) accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of one-set receive data rises last. figure 11.4.1 shows the relationship between the transfer clock and receive data. fig. 11.4.1 relationship between transfer clock and receive data <1st-8data-1sp> st d 0 d 7 sp d 0 st d 7 sp at the falling edge of st, the transfer clock is generated, and reception starts. when the transfer rate of the receive data is faster than the rate of the transfer clock on the receiver side when the transfer rate of the receive data is slower than the rate of the transfer clock on the receiver side rxd i (receive data) transfer clock (receiver side) 1 clock 8 clocks 1 clock 9.5 clocks st : start bit sp : stop bit ? 1 period of brgi s count source (maximum) according to the condition of the input timing, a maximum of this period ( ? ) can be omitted. ? sp must be detected at this last rising edge of the transfer clock. accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula in order to receive data correctly. br: transfer rate on receiver side (bps) bt: transfer rate on transmitter side (bps) f : brgi s count source frequency on receiver side (hz) b : entire bit number of one-set data (ex: 12 bits in the case of 1st-8data-1par-2sp; see figure 11.4.2.) 1 bt 1 f 1 f 1 br 1 bt ? (b 1) + ? (b 0.5) + ? b < < be sure to satisfy the above formula, and set the timing with enough margin. also, the user shall make sufficient evaluation before actually using it.
7906 group user s manual rev.2.0 11-39 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.2 transfer data format the transfer data format can be selected from formats shown in figure 11.4.2. bits 4 to 6 at addresses 30 16 and 38 16 select the transfer data format. (see figure 11.2.2.) set the same transfer data format for both transmitter and receiver sides. figure 11.4.3 shows an example of transfer data format. table 11.4.5 lists each bit in transmit data. transfer data length of 7 bits 1st?data 1sp 1st?data 2sp 1st?data?par1sp 1st?data?par2sp transfer data length of 8 bits 1st?data 1sp 1st?data 2sp 1st?data?par1sp 1st?data?par2sp transfer data length of 9 bits 1st?data 1sp 1st?data 2sp 1st?data?par1sp 1st?data?par2sp st : start bit data : c haracter bit (transfer data) par : parity bit sp : stop bit fig. 11.4.2 transfer data format name st start bit data character bit par parity bit sp stop bit functions l signal equivalent to 1 character bit. this is added immediately before the character bits. it indicates start of data transmission. transmit data which is set in the uarti transmit buffer register. a signal that is added immediately after the character bits in order to improve data reliability. the level of this signal changes according to selection of odd/even parity in such a way that the sum of 1 s in the sum of this bit and character bits is always an odd or even number. h level signal equivalent to 1 or 2 character bits. this is added immediately after the character bits (or parity bit when parity is enabled). it indicates completion of data transmission. fig. 11.4.3 example of transfer data format table 11.4.5 each bit in transmit data time 1st 8data 1par 1sp st lsb msb par sp st transmit/receive data data (8 bits) next transmit/receive data (when continuously transferred)
serial i/o 7906 group user s manual rev.2.0 11-40 11.4 clock asynchronous serial i/o (uart) mode 11.4.3 method of transmission figure 11.4.4 shows an initial setting example for relevant registers when transmitting. the difference depending on the transfer data length (7 bits, 8 bits, or 9 bits) is the transmit data s length only. when selecting a 7- or 8-bit data length, be sure to set the transmit data into the low-order byte of the uarti transmit buffer register. when selecting a 9-bit data length, be sure to set the transmit data into the low-order byte and bit 0 of the high-order byte. transmission is started when all of the following conditions ( ? to ? ) are satisfied: ? transmit data is present in the uarti transmit buffer register (transmit buffer empty flag = 0 ). ? transmit is enabled (transmit enable bit = 1 ). ? the cts i pin s input level is l (when the cts function selected). note: when the cts function is not selected, condition ? is ignored. by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section ?1.4.6 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to ?hapter 6. interrupts. figure 11.4.5 shows writing data after transmission is started, and figure 11.4.6 shows detection of transmit completion.
7906 group user s manual rev.2.0 11-41 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.4 initial setting example for relevant registers when transmitting (if the cts function selected, transmission starts when the cts i pin s input level becomes l. ) 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission enabled transmission starts . uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. b7 b0 transmit data is set. b8 uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external cloc k 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length select bit 0: 1 stop bit 1: 2 stop bit s odd/even parity select bit 0: odd parity 1: even parit y parity enable bit 0: parity is disabled. 1: parity is enabled. sleep select bit 0: sleep mode cleared (invalid) 1: sleep mode selected 1 b2 b1 b0 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bit s cts/rts function is select bit 0: cts function selected 1: rts function selecte d 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b0 b1 5 0 0 cts/rts enable bit 0: cts/rts function is enabled. 1: cts/rts function is disabled. note: the clk i pin cannot be used when the cts i /rts i separation is selected. (refer to [precaution for clock asynchronous serial i/o (uart) mode]. ) serial i/o mode select bit serial i/o pin control register (address ac 16 ) b7 b0 cts 0 /rts 0 separate select bit 0: cts 0 /rts 0 are used together. 1: cts 0 /rts 0 are separated (note) . cts 1 /rts 1 separate select bit 0: cts 1 /rts 1 are used together. 1: cts 1 /rts 1 are separated (note) . txd 0 /p1 3 switch bit 0: functions as txd 0 . txd 1 /p1 7 switch bit 0: functions as txd 1 . 0 port p1 direction register (address 5 16 ) b7 b0 pin cts 0 0 pin cts 1 cts i /rts i are used together. cts i /rts i are separated.
serial i/o 7906 group user s manual rev.2.0 11-42 11.4 clock asynchronous serial i/o (uart) mode [when not using interrupts] [when using interrupts] a uarti transmit interrupt request occurs when the transmission starts. (when the uarti transmit buffer register becomes empty.) uarti transmit interrupt note: uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) b7 b0 writing of next transmit dat a transmit data is set . b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 transmit buffer empty flag 0: data is present in transmit buffer register. 1: no data is present in transmit buffer register. (writing of next transmit data is possible.) checking state of uarti transmit buffer register 1 this figure shows the bits and registers required for processing. see figures 11.4.7 to 11.4.9 for the change of flag state and the occurrence timing of an interrupt request . b0 b8 b15 fig. 11.4.5 write operation of data after transmission start
7906 group user s manual rev.2.0 11-43 serial i/o 11.4 clock asynchronous serial i/o (uart) mode [when not using interrupts] [when using interrupts] uarti transmit interrupt uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b 0 interrupt request bit checking start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 checking completion of transmission. transmit register empty flag 0: transmission is in progress. 1: transmission is completed. processing at completion of transmission 0: no interrupt requested 1: interrupt requested (transmission has started.) a uarti transmit interrupt request occurs when the transmission starts. note: this figure shows the bits and registers required for processing. see figures 11.4.7 to 11.4.9 for the change of flag state and the occurrence timing of an interrupt request. 00 fig. 11.4.6 detect operation of transmit completion
serial i/o 7906 group user s manual rev.2.0 11-44 11.4 clock asynchronous serial i/o (uart) mode 11.4.4 transmit operation when the receive conditions described in section 11.4.3 method of transmission have been satisfied, a transfer clock is generated, and the following operations are automatically performed after 1 cycle of the transfer clock or less has passed. the uarti transmit buffer register s contents are transferred to the uarti transmit register. the transmit buffer empty flag is set to 1. the transmit register empty flag is cleared to 0. a uarti transmit interrupt request occurs, and the interrupt request bit is set to 1. the transmit operations are described below: ? data in the uarti transmit register is transmitted from the txd i pin. ? this data is transmitted bit by bit sequentially in order of st data (lsb) data (msb) par sp according to the transfer data format. ? the transmit register empty flag is set to 1 at the center of the stop bit (or the second stop bit if 2 stop bits selected). this indicates completion of transmission. additionally, whether the transmit conditions for the next data are satisfied or not is examined. when the transmit conditions for the next data are satisfied in step ? , the start bit is generated following the stop bit, and the next data is transmitted. when performing transmission continuously, be sure to set the next transmit data in the uarti transmit buffer register during transmission (i.e. when the transmit register empty flag = 0 ). when the transmit conditions for the next data are not satisfied, the txd i pin outputs h level and the transfer clock stops. figures 11.4.7 and 11.4.8 show examples of transmit timing when the transfer data length = 8 bits, and figure 11.4.9 shows an example of transmit timing when the transfer data length = 9 bits.
7906 group user s manual rev.2.0 11-45 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.8 example of transmit timing when transfer data length = 8 bits (when parity enabled, 1 stop bit and selecting cts function selected) fig. 11.4.7 example of transmit timing when transfer data length = 8 bits (when parity enabled, 1 stop bit selected, cts function not selected) tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p st sp t endi txd i t endi : next transmit conditions are examined when this signal level becomes h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc: 16 (n + 1)/f i or 16 (n + 1)/f ext f i : brgi s count source frequency (internal clock) f ext : brgi s count source frequency (external clock) n: value set in brgi transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. cleared to 0 when interrupt request is accepted or cleared to 0 by software. the above timing diagram applies when the following conditions are satisfied: parity enabled 1 stop bit cts function not selected uarti transmit register uarti transmit buffer register stopped because transmit enable bit = 0 st: start bit d 0 to d 7 : transfer data p: parity bit st: stop bit the above timing diagram applies when the following conditions are satisfied: parity enabled 1 stop bit cts function selected tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp st t endi txd i t endi : next transmit conditions are examined when this signal level becomes h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = 16 (n + 1)/f i or 16 (n + 1)/f ext f i : brgi s count source frequency (internal clock) f ext : brgi s count source frequency (external clock) n: value set in brgi transfer clock transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. cleared to 0 when interrupt request is accepted or cleared to 0 by software. uarti transmit register uarti transmit buffer register transmit enable bit cts i stopped because cts i = h st: start bit d 0 to d 7 : transfer data p: parity bit st: stop bit stopped because transmit enable bit = 0
serial i/o 7906 group user s manual rev.2.0 11-46 11.4 clock asynchronous serial i/o (uart) mode the above timing diagram applies when the following conditions are satisfied: parity disabled 2 stop bits cts function not selected d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 0 d 1 st d 8 sp sp sp tc t endi txd i t endi : next transmit conditions are examined when this signal level becomes h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = 16 (n + 1)/f i or 16 (n + 1)/f ext f i : brgi count source frequency (internal clock) f ext : brgi count source frequency (external clock) n: value set in brgi transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. cleared to 0 when interrupt request is accepted or cleared to 0 by software. uarti transmit register uarti transmit buffer register stopped because transmit enable bit = 0 st: start bit d 0 to d 7 : transfer data p: parity bit st: stop bit fig. 11.4.9 example of transmit timing when transfer data length = 9 bits (when parity disabled, 2 stop bits selected, cts function not selected)
7906 group user s manual rev.2.0 11-47 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.5 method of reception figure 11.4.10 shows an initial setting example for relevant registers when receiving. reception is started when all of the following conditions ( ? and ? ) have been satisfied: ? reception is enabled (receive enable bit = 1 ). ? the start bit (its falling edge) is detected. by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section 11.4.6 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to chapter 6. interrupts. figure 11.4.11 shows processing after reception is completed.
serial i/o 7906 group user s manual rev.2.0 11-48 11.4 clock asynchronous serial i/o (uart) mode reception will start when the start bit ( s falling edge) is detected. port p1 direction register (address 5 16 ) b7 b0 0 0 pin rxd 0 pin rxd 1 uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. ? set the same transfer data format as that of the transmitter side. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 receive enable bit 1: reception enabled uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external cloc k 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length select bit 0: 1 stop bit 1: 2 stop bit s odd/even parity select bit 0: odd parity 1: even parity parity enable bit 0: parity is disabled. 1: parity is enabled. sleep select bit 0: sleep mode cleared (invalid) 1: sleep mode selected 1 b2 b1 b0 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bit s cts/rts function select bit 0: cts function selected 1: rts function selecte d 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b0 0 0 cts/rts enable bit 0: cts/rts function is enabled. 1: cts/rts function is disabled. notes 1: the clk i pin cannot be used when the cts i /rts i separation is selected. (refer to [precau- tion for clock asynchronous serial i/o (uart) mode]. ) 2: when performing reception only, if these bits are set to 1, the txdi pin can be used as a programmable i/o port pin . uarti receive interrupt mode select bit 0: reception interrupt 1: reception error interrupt serial i/o mode select bit serial i/o pin control register (address ac 16 ) b7 b0 cts 0 /rts 0 separate select bit 0: cts 0 /rts 0 are used together. 1: cts 0 /rts 0 are separated (note 1) . cts 1 /rts 1 separate select bit 0: cts 1 /rts 1 are used together. 1: cts 1 /rts 1 are separated (note 1) . txd 0 /p1 3 switch bit (note 2) 0: functions as txd 0 . 1: functions as p1 3 . txd 1 /p1 7 switch bit (note 2) 0: functions as txd 1 . 1: functions as p1 7 . fig. 11.4.10 initial setting example for relevant registers when receiving
7906 group user s manual rev.2.0 11-49 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.11 processing after reception is completed [when not using interrupts] [when using interrupts] a uarti receive interrupt request occurs when reception is completed. uarti receive interrupt processing after reading out receive data uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) b15 b8 reading of receive data read out receive data. b7 b 0 0 0 0 0 0 0 0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b 0 receive complete flag 0 : reception not completed 1 : reception completed checking completion of reception 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 checking error framing error flag parity error flag error sum flag 0 : no error 1 : error detecte d 1 notes 1: when performing the processing after the reception is completed, using an interrupt, be sure to select the receive interrupt (uarti receive interrupt mode select bit = 0 ). 2: this figure shows the bits and registers required for the processing. see figure 11.4.13 for the change of flag state and the occurrence timing of an interrupt request. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 checking error overrun error flag 0 : no overrun error 1 : overrun error detecte d 1 ( note 1 )
serial i/o 7906 group user s manual rev.2.0 11-50 11.4 clock asynchronous serial i/o (uart) mode 11.4.6 receive operation when the receive enable bit is set to 1, the uarti enters the receive-enabled state. then, reception will start when st ( s falling edge) is detected and a transfer clock is generated. if the rts function selected, when connecting the rts i pin to the cts i pin of the transmitter side, the timing of transmission and that of reception can be matched. if the rts function selected, the rts i pin s output level becomes as described below. when the receive enable bit = 0, if one of the following is performed, the rts i pin s output level becomes l and informs of the transmitter side that reception has become enabled: the receive enable bit is set to 1. the low-order byte of the uarti receive buffer register is read out. when the receive enable bit = 1, if the low-order byte of the uarti receive buffer register is read out, the rts i pin s output level becomes l. accordingly, when performing reception continuously, an overrun occurrence can be avoided because the rts output level does not become l until the receive data is read out. when reception has started, the rts i pin s output level becomes h. figure 11.4.12 shows a connection example. fig. 11.4.12 connection example the receive operation is described below. ? the signal input to the rxd i pin is taken into the most significant bit of the uarti receive register, synchronously with the transfer clock s rising edge. ? the contents of the uarti receive register are shifted, bit by bit, to the right. ? steps ? and ? are repeated at each rising edge of the transfer clock. ? when one set of data has been prepared, in other words, when the shift operation has been performed several times according to the selected data format, the uarti receive register s contents are transferred to the uarti receive buffer register. ? simultaneously with step ? , the receive complete flag is set to 1. additionally, when the receive interrupt is selected (uarti receive interrupt mode select bit = 0 ), a uarti receive interrupt request occurs and its interrupt request bit is set to 1. the receive complete flag is cleared to 0 when the low-order byte of the uarti receive buffer register has been read out. figure 11.4.13 shows an example of receive timing when the transfer data length = 8 bits. txd i rxd i txd i rxd i transmitter side receiver side cts i rts i
7906 group user s manual rev.2.0 11-51 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.13 example of receive timing when transfer data length = 8 bits (when parity disabled, 1 stop bit and rts function selected) d 0 d 1 d 7 start bit sampled l received data taken in brgi s count source receive enable bit rxd i transfer clock receive complete flag rts i stop bit the above timing diagram applies when the following conditions are satisfied: parity disabled 1 stop bit rts function selected uarti receive interrupt request bit cleared to 0 when interrupt request is accepted or cleared to 0 by software. uarti receive register uarti receive buffer register at falling edge of start bit, the transfer clock is generated and reception started. uarti receive buffer register s reading out
serial i/o 7906 group user s manual rev.2.0 11-52 11.4 clock asynchronous serial i/o (uart) mode 11.4.7 processing on detecting error in the uart mode, 3 types of errors can be detected. each error can be detected when the data in the uarti receive register is transferred to the uarti receive buffer register, and the corresponding error flag is set to 1. when any error occurs, the error sum flag is set to 1. accordingly, presence of errors can be judged by using the error sum flag. table 11.4.6 lists the conditions for setting each error flag to 1 and method to clear it to 0. additionally, when the receive error interrupt is selected (uarti receive interrupt mode select bit = 1 ), the uarti receive interrupt request bit is set to 1 only when each error has occurred. when the receive interrupt is selected (uarti receive interrupt mode select bit = 0 ), the uarti receive interrupt request bit is set to 1 when reception has been completed or when a framing or parity error has occurred. (even when an overrun error has occurred, this bit does not change). table 11.4.6 conditions for setting each error flag to 1 and method to clear it to 0 method to clear clear the receive enable bit to 0. clear the receive enable bit to 0. read out the low-order byte of the uarti receive buffer register. clear the receive enable bit to 0. read out the low-order byte of the uarti receive buffer register. clear the all error flags, which are overrun, framing and parity error flags. error flag overrun error flag framing error flag parity error flag error sum flag conditions for setting when the next data is prepared in the uarti receive register with the receive complete flag = 1 (i.e. data is present in the uarti receive buffer register). in other words, when the next data is prepared before the contents of the uarti receive buffer register are read out (note). when the number of detected stop bits does not match the set number of stop bits. when the sum of 1 s in the sum of the parity bit and character bits does not match the set number of 1 s. when any error listed above has occurred. note: the next data is written into the uarti receive buffer register. when an error occurs during reception, be sure to initialize the error flag and the uarti receive buffer register, and then perform reception again. when it is necessary to perform retransmission owing to an error which has occurred on the receiver side during transmission, be sure to set the uarti transmit buffer register again, and then perform the retransmission. the method to initialize the uarti receive buffer register and that to set the uarti transmit buffer register again are described below. (1) method to initialize uarti receive buffer register ? clear the receive enable bit to 0 (reception disabled). ? set the receive enable bit to 1 again (reception enabled). (2) method to set uarti transmit buffer register again ? clear the serial i/o mode select bits to 000 2 (serial i/o invalid). ? set the serial i/o mode select bits again. ? set the transmit enable bit to 1 (transmission enabled), and set the transmit data to the uarti transmit buffer register.
7906 group user s manual rev.2.0 11-53 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.8 sleep mode this mode is used to transfer data between the specified microcomputers, which are connected by using uarti. the sleep mode is selected by setting the sleep select bit (bit 7 at addresses 30 16 , 38 16 ) to 1 when receiving. in the sleep mode, receive operation is performed when the msb (d 8 when the transfer data = 9-bit length, d 7 when it is 8-bit length, d 6 when it is 7-bit length) of the receive data is 1. receive operation is not performed when the msb is 0. (the uarti receive register s contents are not transferred to the uarti receive buffer register. additionally, the receive complete flag and each error flag do not change, and no uarti receive interrupt request occurs.) the following shows an usage example of the sleep mode when the transfer data = 8-bit length. ? be sure to set the same transfer data format for the master and slave microcomputers. additionally, be sure to select the sleep mode for the slave microcomputers. ? then, transmit the data, of which structure is as follows, from the master microcomputer: bit 7 = 1 bits 6 to 0 indicate the address of the slave microcomputer to be communicated ? each slave microcomputer receives the data described in step ? . (at this time, a uarti receive interrupt request occurs.) ? be sure to check for each slave microcomputer, in the interrupt routine, whether bits 6 to 0 of the receive data match its own address. ? for the slave microcomputer of which address matches bits 6 to 0 of the receive data, terminate the sleep mode. (do not terminate the sleep mode for the other slave microcomputers.) by performing steps ? to ? , the microcomputer which performs transfer is specified. ? transmit the data of which bit 7 = 0 from the master microcomputer. (only one slave microcomputer specified in steps ? to ? can receive this data. the other microcomputers do not receive this data.) ? by repeating step ? , continuous transfer can be performed between two specific microcomputers. when communicating with another slave microcomputer, perform steps ? to ? in order to specify the new slave microcomputer. fig. 11.4.14 sleep mode master slave b slave a slave d slave c data is transferred between the master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers.
serial i/o 7906 group user s manual rev.2.0 11-54 [precautions for clock asynchronous serial i/o (uart) mode] [precautions for clock asynchronous serial i/o (uart) mode] 1. when separating cts i /rts i , the clk i pin cannot be used. accordingly, when separating cts i /rts i in uart mode, be sure to select an internal clock. 2. writing to the uarti baud rate register (brgi) must be performed while transmission/reception halts. 3. when transmitting, be sure to clear the txd 0 /p1 3 or txd 1 /p1 7 switch bit (bits 2, 3 at address ac 16 ) to 0.
chapter 12 a-d converter 12.1 overview 12.2 block description 12.3 a-d conversion method 12.4 absolute accuracy and differential non-linearity error 12.5 comparison voltage in 8-bit resolution mode 12.6 comparator function 12.7 one-shot mode 12.8 repeat mode 12.9 single sweep mode 12.10 repeat sweep mode 0 [precautions for a-d converter]
a-d converter 7906 group user? manual rev.2.0 12-2 12.1 overview 12.1 overview the a-d conversion is performed in the 8-bit resolution mode or the 10-bit resolution mode. also, the input voltage can be compared with the set value by using the a-d converter (in other words, the comparator function). whether to perform the a-d conversion or comparison can be selected for each pin. ? in chapter 12, the operations common to the a-d converter? functions (8-bit resolution, 10-bit resolution, comparator) are simply referred to as ?peration. table 12.1.1 lists the performance specifications of the a-d converter. table 12.1.1 performance specifications of a-d converter item performance specifications a-d conversion method successive approximation conversion method resolution either of 8-bit or 10-bit resolution can be selected by software. absolute accuracy 8-bit resolution mode : ? lsb 10-bit resolution mode : ? lsb analog input pin (note) 5 pins (an 0 to an 4 ) conversion rate per analog input pin 8-bit resolution mode : 49 ad cycles 10-bit resolution mode : 59 ad cycles ad : a-d converter? operation clock note: for each of analog input pin an i (i = 0 to 4), whether to use pin an i as an input pin of the a-d converter or as that of the comparator can be selected by using the comparator function select register 0 (address dc 16 ). (1) 8-bit resolution mode the input voltage from pin an i (i = 0 to 4) is a-d converted, and the 8-bit a-d conversion result is stored in a-d register i. (refer to sections ?2.3 a-d conversion method? and ?2.5 comparison voltage in 8-bit resolution mode. ) (2) 10-bit resolution mode the input voltage from pin an i is a-d converted, and the 10-bit a-d conversion result is stored in a-d register i. (refer to section ?2.3 a-d conversion method. ) (3) comparator function the 8-bit value which has been set in a-d register i is compared with the voltage input from pin an i ; and then, the result of comparison is stored into the an i pin comparator result bit. (refer to section ?2.6 comparator function. ) comparator function comparison operation comparison between the set value and analog input voltage comparison rate per 14 ad cycles analog input pin
a-d converter 7906 group user? manual rev.2.0 12-3 (4) operation modes the a-d converter is equipped with the following 4 modes. the a-d conversion and comparison (in other words, the comparator function) are performed in the same operation modes. one-shot mode this mode is used to perform the operation once for a voltage input from one selected analog input pin. repeat mode this mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin. single sweep mode this mode is used to perform the operation for voltages input from multiple selected analog input pins, one at a time. repeat sweep mode 0 this mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins. 12.1 overview
a-d converter 7906 group user? manual rev.2.0 12-4 12.2 block description 12.2 block description figure 12.2.1 shows the block diagram of the a-d converter. registers relevant to the a-d converter are described below. fig. 12.2.1 block diagram of a-d converter ad a-d conversion frequency ( ad ) select bits 1, 0 (1,1) selection of a-d conversion frequency f 2 (1,0) (0,1) (0,0) 1/2 1/2 f 1 comparator av ss resistor ladder network selector an 0 an 1 an 2 an 3 an 4 decoder data bus (odd) v ref v ref comparator function select register 0 selector selector comparator result register 0 control circuit successive approximation register a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 1 a-d control register 1 a-d control register 0 0 1 v ref connection select bit data bus (even)
a-d converter 7906 group user s manual rev.2.0 12-5 fig. 12.2.2 structure of a-d control register 0 12.2.1 a-d control registers 0, 1 figures 12.2.2 and 12.2.3 show the structures of the a-d control registers 0 and 1. 12.2 block description undefined undefined undefined 0 0 0 0 0 rw rw rw rw rw rw rw (note 4) rw notes 1: these bits are invalid in the single sweep mode and repeat sweep mode 0. (each may be either 0 or 1. ) 2: when using pin an 3 , be sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: when using pin an 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 4: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 5: writing to each bit (except writing of 0 to bit 6) of the a-d control register 0 must be performed while the a-d converter halts, regardless of the a-d operation mode. 0 1 2 3 4 5 6 7 a-d control register 0 (address 1e 16 ) analog input pin select bits (valid in the one-shot and repeat modes.) (note 1) a-d operation mode select bits fix this bit to 0. a-d conversion start bit a-d conversion frequency ( ad ) select bit 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : an 0 is selected. 0 0 1 : an 1 is selected. 0 1 0 : an 2 is selected. 0 1 1 : an 3 is selected. (note 2) 1 0 0 : an 4 is selected. (note 3) 1 0 1 : do not select. 1 1 0 : do not select. 1 1 1 : do not select. b2 b1 b0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 b4 b3 bit name bit function at reset r/w 0 : a-d conversion halts. 1 : a-d conversion starts. see table 12.2.1. 0
a-d converter 7906 group user s manual rev.2.0 12-6 fig. 12.2.3 structure of a-d control register 1 12.2 block description 0 1 2 3 4 5 6 7 undefined undefined 0 0 0 0 0 0 rw rw rw rw rw rw rw a-d control register 1 (address 1f 16 ) a-d sweep pin select bits (valid in the single sweep mode and repeat sweep mode 0.) (note 1) fix this bit to 0. resolution select bit a-d conversion frequency ( ad ) select bit 1 fix this bit to 0. v ref connection select bit (note 4) the value is 0 at reading. b7 b6 b5 b4 b3 b2 b1 b0 0 0 : pins an 0 and an 1 (2 pins) 0 1 : pins an 0 to an 3 (4 pins) (note 2) 1 0 : pins an 0 to an 4 (5 pins) (notes 2, 3) 1 1 : do not select. b1 b0 0 : 8-bit resolution mode 1 : 10-bit resolution mode see table 12.2.1. 0 0 : pin v ref is connected. 1 : pin v ref is disconnected. bit name bit function at reset r/w notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1. ) 2: when using pin an 3 , be sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: when using pin an 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 4: when this bit is cleared from 1 to 0, be sure to start the a-d conversion after an interval of 1 s or more has elapsed. 5: writing to each bit of the a-d control register 1 must be performed while the a-d converter halts, regardless of the a-d operation mode. 0
a-d converter 7906 group user s manual rev.2.0 12-7 12.2 block description (1) analog input pin select bits (bits 0 to 2 at address 1e 16 ) these bits are used to select an analog input pin in the one-shot mode or repeat mode. pins which are not selected as analog input pins serve as programmable i/o port pins. also, these bits must be specified again if the user switches the operation mode to the one-shot mode or repeat mode after the operation is performed in the single sweep mode or repeat sweep mode 0. (2) a-d operation mode select bits (bits 3 and 4 at address 1e 16 ) these bits are used to select the operation mode of the a-d converter. (3) a-d conversion start bit (bit 6 at address 1e 16 ) setting this bit to 1 generates a trigger, causing the a-d converter to start its operation. clearing this bit to 0 causes the a-d converter to halt its operation. in the one-shot mode or single sweep mode, this bit is cleared to 0 when the operation is completed. in the repeat mode or repeat sweep mode 0, the a-d converter continues its operation until this bit is cleared to 0 by software. (4) a-d conversion frequency ( ad ) select bit 0 (bit 7 at address 1e 16 ), a-d conversion frequency ( ad ) select bit 1 (bit 4 at address 1f 16 ) these bits are used to select the operation clock ( ad ) of the a-d converter. table 12.2.1 lists the conversion time per one analog input pin. since the a-d converter s comparator consists of capacity coupling amplifiers, be sure to keep that ad 250 khz while the a-d converter is active. (5) a-d sweep pin select bits (bits 0 and 1 at address 1f 16 ) these bits are used to select analog input pins in the single sweep mode or repeat sweep mode 0. pins which are not selected as analog input pins serve as programmable i/o port pins or as i/o pins of other internal peripheral devices, which are multiplexed. (6) resolution select bit (bit 3 at address 1f 16 ) this bit is used to select a resolution. (7) v ref connection select bit (bit 6 at address 1f 16 ) when the a-d converter is not used, this bit is used to disconnect the resistor ladder network of the a-d converter from the reference voltage input pin (v ref ). when the resistor ladder network is disconnected from pin v ref , the current is not flowed from pin v ref to resistor ladder network. accordingly, the power dissipation can be saved. when this bit changes from 1 (v ref disconnected) to 0 (v ref connected), start of the operation must be 1 s or more later. 0 0 1 1 8-bit resolution mode 10-bit resolution mode f sys = 20 mhz conversion time ( s) (note) ad 0 1 0 1 f 2 divided by 4 f 2 divided by 2 f 2 f 1 19.60 9.80 4.90 2.45 a-d conversion frequency ( ad ) select bit 1 a-d conversion frequency ( ad ) select bit 0 23.60 11.80 5.90 comparator function do not select. 5.60 2.80 1.40 0.70 note: this applies when the peripheral devices clock select bits 0, 1 (bits 6, 7 at address bc 16 ) = 00 2 . table 12.2.1 conversion time per one analog input pin
a-d converter 7906 group user s manual rev.2.0 12-8 12.2 block description 12.2.2 a-d register i (i = 0 to 4) figure 12.2.4 shows the structure of the a-d register i. when the a-d conversion is completed, the conver- sion result (contents of the successive approximation register) is stored into this register. when the comparator function is selected, the value to be compared is stored in this register. each a-d register i corresponds to an analog input pin (an i ). fig. 12.2.4 structure of a-d register i undefined 0 ro bit 7 to 0 15 to 8 function at reset r/w reads an a-d conversion result. the value is 0 at reading. b0 b7 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) b0 b7 (b15) (b8) when 8-bit resolution mode is selected a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) when 10-bit resolution mode is selected undefined 0 ro 9 to 0 15 to 10 reads an a-d conversion result. the value is 0 at reading. b0 b7 b0 b7 (b15) (b8) bit function at reset r/w a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) when comparator function is selected undefined 0 ro 7 to 0 15 to 8 any value in the range from 00 16 to ff 16 can be set. the set value is compared with the input voltage. the value is undefined at reading. the value is 0 at reading. b0 b7 b0 b7 (b15) (b8) bit function at reset r/w note: when the comparator function is selected, writing to and reading from a-d register i must be performed while the a-d converter halts.
a-d converter 7906 group user s manual rev.2.0 12-9 12.2 block description 12.2.3 comparator function select register 0, comparator result register 0 figure 12.2.5 shows the structure of comparator function select register 0; figure 12.2.6 shows the structure of comparator result register 0. when the an i pin comparator function select bit is set to 1, the comparator function is selected. when the a-d conversion is performed, be sure to clear the corresponding bit to 0. for details of the comparator function, refer to section ?2.6 comparator function. fig. 12.2.5 structure of comparator function select register 0 fig. 12.2.6 structure of comparator result register 0 bit name bit 0 1 2 3 4 7 to 5 comparator function select register 0 (address dc 16 ) function at reset r/w an 0 pin comparator function select bit an 1 pin comparator function select bit an 2 pin comparator function select bit an 3 pin comparator function select bit an 4 pin comparator function select bit fix these bits to 000. 0 0 0 0 0 0 rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : the comparator function is not selected. 1 : the comparator function is selected. 00 0 note: writing to comparator function select register 0 must be performed while the a-d converter halts. b7 b6 b5 b4 b3 b2 b1 b0 note: writing to comparator result register 0 must be performed while the a-d converter halts. bit name bit 0 1 2 3 4 7 to 5 comparator result register 0 (address de 16 ) function at reset r/w an 0 pin comparator result bit an 1 pin comparator result bit an 2 pin comparator result bit an 3 pin comparator result bit an 4 pin comparator result bit fix these bits to 000. 0 0 0 0 0 0 rw rw rw rw rw rw 0 : the set value > the input level at pin an i 1 : the set value < the input level at pin an i 000
a-d converter 7906 group user s manual rev.2.0 12-10 12.2.4 a-d conversion interrupt control register figure 12.2.7 shows the structure of the a-d conversion interrupt control register. for details about interrupts, refer to ?hapter 6. interrupts. (1) interrupt priority level select bits (bits 2 to 0) these bits are used to select an a-d conversion interrupt s priority level. when using an a-d conversion interrupt, be sure to select one of the priority levels (1 to 7). when an a-d conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0. ) to disable an a-d conversion interrupt, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when an a-d conversion interrupt request has occurred. this bit is automatically cleared to 0 when the a-d conversion interrupt request has accepted. this bit can be set to 1 or cleared to 0 by software. 12.2 block description 0 1 2 3 7 to 4 a-d conversion interrupt control register (address 70 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt priority level select bits interrupt request bit nothing is assigned. notes 1: before using an a-d conversion interrupt, be sure to clear this bit to 0 by software. 2: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 0 0 undefined (note 1) undefined rw rw rw rw (note 2) bit name bit function at reset r/w fig. 12.2.7 structure of a-d conversion interrupt control register
a-d converter 7906 group user s manual rev.2.0 12-11 12.2 block description 12.2.5 port p7 direction register the a-d converter s input pins are multiplexed with the port p7 pins. when using these pins as a-d converter s input pins, be sure to clear the corresponding bits of the port p7 direction register to 0 in order to set these pins to the input mode. figure 12.2.8 shows the correspondence between the port p7 direction register and the a-d converter s input pins. 0 1 2 3 4 7 to 5 port p7 direction register (address 11 16 ) pin an 0 pin an 1 pin an 2 pin an 3 (pin da 0 ) (note 1) pin an 4 (pin da 1 /int 3 /rtp trg0 ) (note 2) nothing is assigned. 0 0 0 0 0 undefined rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode 1 : output mode when using any of these pins as a-d converter s input pin, be sure to clear its corresponding bit to 0. notes 1: when using pin an 3 , be sure to clear the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 2: when using pin an 4 , be sure to clear the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 3: the pins in ( ) are i/o pins of other internal peripheral devices, which are multiplexed with the corresponding port p7 pins. bit name bit function at reset r/w fig. 12.2.8 correspondence between port p7 direction register and a-d converter? input pins
a-d converter 7906 group user s manual rev.2.0 12-12 12.3 a-d conversion method 12.3 a-d conversion method the a-d converter compares the comparison voltage (v ref ), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (v in ), which is input from the analog input pin (an i ). by reflecting the comparison result on the successive approximation register, v in is converted into a digital value. when a trigger is generated, the a-d converter performs the following processing: ? determining bit 9 of the successive approximation register the a-d converter compares v ref with v in . at this time, the contents of the successive approximation register is 1000000000 2 (initial value). bit 9 of the successive approximation register depends on the comparison result as follows: when v ref < v in , bit 9 = 1 when v ref > v in , bit 9 = 0 ? determining bit 8 of the successive approximation register after setting bit 8 of the successive approximation register to 1, the a-d converter compares v ref with v in . bit 8 depends on the comparison result as follows: when v ref < v in , bit 8 = 1 when v ref > v in , bit 8 = 0 ? determining bits 7 to lsb of the successive approximation register operation ? is performed for each of bits 7 to 0 in the 10-bit resolution mode. operation ? is performed for each of bits 7 to 2 in the 8-bit resolution mode. when the lsb is determined, the contents of the successive approximation register (in order words, conversion result) are transferred to the a-d register i. v ref is generated according to the latest contents of the successive approximation register. table 12.3.1 lists the relationship between the successive approximation register s contents and v ref . tables 12.3.2 and 12.3.3 list the changes of the successive approximation register and v ref during the a-d conversion, respectively. figure 12.3.1 shows the ideal a-d conversion characteristics in the 10-bit resolution mode. successive approximation register s contents: n 0 v ref 1024 1 to 1023 (n 0.5) v ref (v) 0 v ref : reference voltage table 12.3.1 relationship between successive approximation register? contents and v ref
a-d converter 7906 group user s manual rev.2.0 12-13 12.3 a-d conversion method table 12.3.2 change of successive approximation register and v ref during a-d conversion (8-bit resolution) table 12.3.3 change of successive approximation register and v ref during a-d conversion (10-bit resolution) 1 1 n 9 0 00000000 000000000 100 000000 n 9 n 8 10000000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 100 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 00 b9 b0 1st comparison result 2nd comparison result successive approximation register change of v ref a-d converter halt 1st comparison 2nd comparison 3rd comparison 8th comparison conversion completed 2 v ref 2048 v ref : 2 v ref 2 v ref 4 v ref 2048 v ref 2 v ref 4 v ref 8 v ref 2048 v ref 2 v ref 4 v ref 8 v ref ...... v ref 256 2048 v ref [v] [v] [v] [v] [v] 4 v ref n 9 = 1 4 v ref n 9 = 0 + 8 v ref 8 v ref n 8 = 1 n 8 = 0 + : : : : : 1 1 n 9 00000 0000 000 000000 100 000000 n 9 n 8 1000 0000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 1 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 b9 b0 2 v ref 2048 v ref 2 v ref 2 v ref 4 v ref 2048 v ref 2 v ref 4 v ref 8 v ref 2048 v ref 2 v ref 4 v ref 8 v ref ...... v ref 1024 2048 v ref [v] [v] [v] [v] [v] successive approximation register change of v ref a-d converter halt 1st comparison 2nd comparison 3rd comparison 10th comparison conversion completed 1st comparison result 2nd comparison result 4 v ref n 9 = 1 4 v ref n 9 = 0 + 8 v ref 8 v ref n 8 = 1 n 8 = 0 + : : : : : :
a-d converter 7906 group user s manual rev.2.0 12-14 fig. 12.3.1 ideal a-d conversion characteristics in 10-bit resolution mode 000 16 001 16 002 16 003 16 3fe 16 3ff 16 analog input voltage v ref 1024 ? 1 v ref 1024 ? 2 v ref 1024 ? 3 ? 1021 v ref 1024 v ref 1024 ? 1022 v ref 1024 ? 1023 v ref v ref 1024 ? 0.5 ldeal a-d conversion characteristics 0 a-d conversion result 3fd 16 12.3 a-d conversion method
a-d converter 7906 group user s manual rev.2.0 12-15 12.4 absolute accuracy and differential non-linearity error fig. 12.4.1 absolute accuracy of a-d converter (10-bit resolution mode) 12.4 absolute accuracy and differential non-linearity error the a-d converter s accuracy is described below. refer to section ?ppendix 10.4 a-d converter standard characteristics, also. 12.4.1 absolute accuracy the absolute accuracy is the difference expressed in the lsb between the actual a-d conversion result and the output code of an a-d converter with ideal characteristics. (see figure 12.4.1 for more details.) the analog input voltage at measurement of the absolute accuracy is assumed to be the mid point of the analog input voltage width that outputs the same output code from an a-d converter with ideal characteristics. for example, in the case of the 10-bit resolution mode, when v ref = 5.12 v, 1 lsb width is 5 mv, and 0 mv, 5 mv, 10 mv, 15 mv, 20 mv, ... are selected as the analog input voltages. the absolute accuracy = 3 lsb indicates that when the analog input voltage is 25 mv, the output code expected from an ideal a-d conversion characteristics is 005 16 , but the actual a-d conversion result is between 002 16 to 008 16 . the absolute accuracy includes the zero error and the full-scale error. the absolute accuracy degrades when v ref is lowered. any of the output codes for analog input voltages in the range from v ref to vcc is 3ff 16 . 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 5 10 1520 253035 4045 5055 007 16 008 16 009 16 00a 16 00b 16 +3 lsb 3 lsb ideal a-d conversion characteristics analog input voltage (mv) output code (a-d conversion result)
a-d converter 7906 group user s manual rev.2.0 12-16 12.4.2 differential non-linearity error the differential non-linearity error indicates the difference between the 1 lsb step width (the ideal analog input voltage width while the same output code is expected to output) of an a-d converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). (see figure 12.4.2 for more details.) for example, in the case of the 10-bit resolution mode and v ref = 5.12 v, the 1 lsb width of an a-d converter with ideal characteristics is 5 mv; but if the differential non-linearity error is 1 lsb, the actual measured 1 lsb width is in the range from 0 to 10 mv. fig. 12.4.2 differential non-linearity error (10-bit resolution mode) 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 5 10 1520 253035 4045 007 16 008 16 009 16 output code (a-d conversion result) differential non-linearity error analog input voltage (mv) 1 lsb width with ideal a-d conversion characteristics 12.4 absolute accuracy and differential non-linearity error
a-d converter 7906 group user? manual rev.2.0 12-17 12.5 comparison voltage in 8-bit resolution mode in the 8-bit resolution mode, which is selected by the resolution select bit, the high-order 8 bits of the 10- bit successive approximation register are treated as the a-d conversion result. accordingly, when compared with the 8-bit a-d converter, a comparison reference voltage is different by 3v ref /2048. (refer to the underlined portions in table 12.5.1). the difference of the output code change point is generated as shown in figure 12.5.1. table 12.5.1 comparison voltage 12.5 comparison voltage in 8-bit resolution mode m37906? 8-bit resolution mode 8-bit a-d converter v ref 2 8 v ref 2 10 ? n v ref 2 8 v ref 2 8 ? n ? 0.5 comparison voltage v ref v ref : reference voltage n : contents of successive approximation register ? 0.5 fig. 12.5.1 difference of output code change point 07 05 06 03 00 02 analog input voltage (mv) 02 01 00 04 02 01 00 01 08 09 10 30 17.5 37.5 8-bit a-d converter s ideal characteristics (when v ref = 5.12 v) output code (a-d conversion result) output code (a-d conversion result) 8-bit resolution mode 10-bit resolution mode (note) analog input voltage (mv) 8-bit resolution mode 10-bit resolution mode note : difference of output code change point v ref : reference voltage (note) m37906 s a-d converter s ideal characteristics (when v ref = 5.12 v)
a-d converter 7906 group user s manual rev.2.0 12-18 12.6 comparator function by setting the an i pin comparator function select bit (see figure 12.2.5.) to 1, the comparator function can be selected for each pin an i . for pin an i where the comparator function is selected, the following comparison operation is performed. ? a 10-bit value (a set value), of which high-order 8 bits consist of the corresponding a-d register i (at an even-numbered address) s contents and of which low-order 2 bits = 10 2 , is d-a converted. ? the result of the d-a conversion (that is to say, comparison voltage v ref ) is compared with an analog voltage input from an analog input pin. ? the value to be stored into the an i pin comparator result bit (see figure 12.2.6.) depends on the comparison result as follows: when v ref > analog input voltage, 0 is stored. when v ref < analog input voltage, 1 is stored. 12.6 comparator function
a-d converter 7906 group user s manual rev.2.0 12-19 12.7 one-shot mode 12.7 one-shot mode in the one-shot mode, the operation for an input voltage from one selected analog input pin is performed once, and an a-d conversion interrupt request occurs at completion of the operation. 12.7.1 settings for one-shot mode figures 12.7.1 and 12.7.2 show initial setting examples for related registers in the one-shot mode. when using an interrupt, it is necessary to set the related registers to enable an interrupt. refer to ?hapter 6. interrupts for more details. fig. 12.7.1 initial setting example for related registers in one-shot mode (1) selection of comparator function b7 b0 comparator function select register 0 (address dc 16 ) 0 : comparator function is not selected . 1 : comparator function is selected. an 0 an 1 an 2 an 3 an 4 when comparator function is selected when comparator function is not selected a-d register i b7 b0 a-d register 0 (addresses 21 16, 20 16 ) a-d register 1 (addresses 23 16, 22 16 ) a-d register 2 (addresses 25 16, 24 16 ) a-d register 3 (addresses 27 16, 26 16 ) a-d register 4 (addresses 29 16, 28 16 ) b7 b0 (b15) (b8) a value (comparison value) in the range from 00 16 through ff 16 is set. continued on figure 12.7.2. b7 b0 a-d control register 0 (address 1e 16 ) 00 0 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected b2 b1 b0 a-d conversion start bit 0 : a-d conversion halts. analog input pin select bits b7 a-d control register 1 (address 1f 16 ) x : it may be either 0 or 1. a-d conversion frequency ( ad ) select bit 0 see table 12.2.1. one-shot mode b0 resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode a-d conversion frequency ( ad ) select bit 1 see table 12.2.1. v ref connection select bit 0 : pin v ref is connected. 0 0 00 x x 0 0 0 a-d control registers 0 and 1
a-d converter 7906 group user s manual rev.2.0 12-20 12.7 one-shot mode fig. 12.7.2 initial setting example for related registers in one-shot mode (2) setting of a-d conversion start bit to 1. b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start bit 1 port p7 direction register b7 b0 port p7 direction register (address 11 16 ) an 0 an 1 an 2 an 3 an 4 operation starts. trigger generated interrupt priority level b7 b0 a-d conversion interrupt control register (address 70 16 ) interrupt priority level select bits set the level to one of 1 through 7 when using this interrupt. set the level to 0 when disabling interrupts. interrupt request bit 0 : no interrupt requested continued from preceding figure 12.7.1 clear the bits, corresponding to the selected analog input pins, to 0. 0 note: writing to the following must be performed while the a-d converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the a-d converter. each bit of the a-d control register 0, except bit 6 each bit of the a-d control register 1 a-d register i (when the comparator function is selected) comparator function select register 0 especially, when the v ref connection select bit is cleared from 1 to 0, an interval of 1 s or more must be elapsed before occurrence of a trigger.
a-d converter 7906 group user s manual rev.2.0 12-21 12.7 one-shot mode 12.7.2 one-shot mode operation ? the a-d converter starts its operation when the a-d conversion start bit is set to 1. ? the a-d conversion is completed after 49 cycles of ad in the 8-bit resolution mode, or 59 cycles of ad in the 10-bit resolution mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. when the comparator function is selected, the comparison is completed after 14 cycles of ad . then, the result of the comparison is stored into the an i pin comparator result bit. ? at the same time as step ? , the a-d conversion interrupt request bit is set to 1. ? the a-d conversion start bit is cleared to 0, and the a-d converter halts. figure 12.7.3 shows the operation in the one-shot mode. fig. 12.7.3 operation in one-shot mode trigger generated convert input voltage at pin an i . a-d converter halts. a-d conversion interrupt request occurs. conversion result a-d register i 8-bit and 10-bit resolution modes comparator function trigger generated compare input voltage at pin an i . a-d converter halts. a-d conversion interrupt request occurs. comparison result an i pin comparator result bit
a-d converter 7906 group user s manual rev.2.0 12-22 12.8 repeat mode 12.8 repeat mode in the repeat mode, the a-d conversion for an input voltage from one selected analog input pin is performed repeatedly. in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the a-d converter repeates its operation while the a-d conversion start bit = 1. 12.8.1 settings for repeat mode figures 12.8.1 and 12.8.2 show initial setting examples for related registers in the repeat mode. fig. 12.8.1 initial setting example for related registers in repeat mode (1) selection of comparator function b7 b0 comparator function select register 0 (address dc 16 ) 0 : comparator function is not selected. 1 : comparator function is selected. an 0 an 1 an 2 an 3 an 4 when comparator function is not selected continued on figure 12.8.2. a-d register i b7 b0 a-d register 0 (addresses 21 16, 20 16 ) a-d register 1 (addresses 23 16, 22 16 ) a-d register 2 (addresses 25 16, 24 16 ) a-d register 3 (addresses 27 16, 26 16 ) a-d register 4 (addresses 29 16, 28 16 ) when comparator function is selected b7 b0 (b15) (b8) a value (comparison value) in the range from 00 16 through ff 16 is set. a-d control registers 0 and 1 b7 b0 a-d control register 0 (address 1e 16 ) 01 0 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected b2 b1 b0 a-d conversion start bit 0 : a-d conversion halts. analog input pin select bits b7 a-d control register 1 (address 1f 16 ) repeat mode b0 resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode a-d conversion frequency ( ad ) select bit 1 see table 12.2.1. v ref connection select bit 0 : pin v ref is connected. x x 0 0 x : it may be either 0 or 1. 00 0 0 0 a-d conversion frequency ( ad ) select bit 0 see table 12.2.1.
a-d converter 7906 group user s manual rev.2.0 12-23 fig. 12.8.2 initial setting example for related registers in repeat mode (2) 12.8 repeat mode operation starts. trigger generated setting of a-d conversion start bit to 1. b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start bit 1 port p7 direction register b7 b0 port p7 direction register (address 11 16 ) clear the bits, corresponding to the selected analog input pins, to 0. an 0 an 1 an 2 an 3 an 4 continued from preceding figure 12.8.1 note: writing to the following must be performed while the a-d converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the a-d converter. each bit of the a-d control register 0, except bit 6 each bit of the a-d control register 1 a-d register i (when the comparator function is selected) comparator function select register 0 especially, when the v ref connection select bit is cleared from 1 to 0, an interval of 1 s or more must be elapsed before occurrence of a trigger.
a-d converter 7906 group user s manual rev.2.0 12-24 12.8 repeat mode 12.8.2 repeat mode operation ? the a-d converter starts its operation when the a-d conversion start bit is set to 1. ? the 1st a-d conversion is completed after 49 cycles of ad in the 8-bit resolution mode, or 59 cycles of ad in the 10-bit resolution mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. when the comparator function is selected, the 1st comparison is completed after 14 cycles of ad . then, the result of the comparison is stored into the an i pin comparator result bit. ? the a-d converter repeats its operation until the a-d conversion start bit is cleared to 0 by software. the conversion result is transferred to the a-d register i each time the conversion is completed. when the comparator function is selected, the comparison result is stored into the an i pin comparator result bit each time the comparison is completed. figure 12.8.3 shows the operation in the repeat mode. fig. 12.8.3 operation in repeat mode trigger generated convert input voltage at pin an i . conversion result a-d register i 8-bit and 10-bit resolution modes comparator function compare input voltage at pin an i . comparison result an i pin comparator result bit trigger generated
a-d converter 7906 group user s manual rev.2.0 12-25 12.9 single sweep mode 12.9 single sweep mode in the single sweep mode, the operation for the input voltages from multiple selected analog input pins are performed, one at a time. the operation is performed in ascending sequence from pin an 0 to pin an 7 . an a-d conversion interrupt request occurs when the operations for all selected analog input pins are completed. 12.9.1 settings for single sweep mode figures 12.9.1 and 12.9.2 show initial setting examples for related registers in the single sweep mode. when using an interrupt, it is necessary to set the related registers to enable an interrupt. refer to chapter 6. interrupts for more details. fig. 12.9.1 initial setting example for related registers in single sweep mode (1) selection of comparator function b7 b0 comparator function select register 0 (address dc 16 ) 0 : comparator function is not selected. 1 : comparator function is selected. an 0 an 1 an 2 an 3 an 4 when comparator function is not selected when comparator function is selected a-d register i b7 b0 a-d register 0 (addresses 21 16, 20 16 ) a-d register 1 (addresses 23 16, 22 16 ) a-d register 2 (addresses 25 16, 24 16 ) a-d register 3 (addresses 27 16, 26 16 ) a-d register 4 (addresses 29 16, 28 16 ) b7 b0 (b15) (b8) a value (comparison value) in the range from 00 16 through ff 16 is set. continued on figure 12.9.2. a-d control registers 0 and 1 b7 b0 a-d control register 0 (address 1e 16 ) 10 0 single sweep mode x xx a-d conversion start bit 0 : a-d conversion halts. a-d conversion frequency ( ad ) select bit 0 see table 12.2.1. a-d sweep pin select bits b1 b0 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 4 (5 pins) b7 a-d control register 1 (address 1f 16 ) b0 0 resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode a-d conversion frequency ( ad ) select bit 1 see table 12.2.1. v ref connection select bit 0 : pin v ref is connected. 0 x : it may be either 0 or 1. 000 0 0
a-d converter 7906 group user s manual rev.2.0 12-26 fig. 12.9.2 initial setting example for related registers in single sweep mode (2) 12.9 single sweep mode setting of a-d conversion start bit to 1. b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start bit 1 interrupt priority level b7 b0 a-d conversion interrupt control register (address 70 16 ) interrupt priority level select bits set the level to one of 1 through 7 when using this interrupt. set the level to 0 when disabling interrupts. port p7 direction register b7 b0 port p7 direction register (address 11 16 ) clear the bits, corresponding to the selected analog input pins, to 0. an 0 an 1 an 2 an 3 an 4 interrupt request bit 0 : no interrupt requested 0 operation starts. trigger generated continued from preceding figure 12.9. 1 note: writing to the following must be performed while the a-d converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the a-d converter. each bit of the a-d control register 0, except bit 6 each bit of the a-d control register 1 a-d register i (when the comparator function is selected) comparator function select register 0 especially, when the v ref connection select bit is cleared from 1 to 0, an interval of 1 s or more must be elapsed before occurrence of a trigger.
a-d converter 7906 group user s manual rev.2.0 12-27 12.9 single sweep mode 12.9.2 single sweep mode operation ? the a-d converter starts its operation for the input voltage at pin an 0 when the a-d conversion start bit is set to 1. ? the a-d conversion for the input voltage at pin an 0 is completed after 49 cycles of ad in the 8- bit resolution mode, or 59 cycles of ad in the 10-bit resolution mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. when the comparator function is selected, the comparison for pin an 0 is completed after 14 cycles of ad . then, the result of the comparison is stored into the an 0 pin comparator result bit. ? the operations for all selected analog input pins are performed. in the 8-bit and 10-bit resolution modes, the conversion result is transferred to the corresponding a-d register i each time when the a-d conversion per one pin is completed. when the comparator function is selected, the comparison result is stored into the an i pin comparator result bit each time the comparison for one pin is completed. ? when step ? is completed, the a-d conversion interrupt request bit is set to 1. ? the a-d conversion start bit is cleared to 0, and the a-d converter halts. note that the operation time for pins an 0 to an 4 is equivalent to the time for 6 pins when the a-d sweep pin select bits (bits 1, 0 at address 1f 16 ) = 10 2 . figure 12.9.3 shows the operation in the single sweep mode. fig. 12.9.3 operation in single sweep mode convert input voltage at pin an i or compare input voltage at pin an i a-d converter halts. a-d converter interrupt request occurs. trigger generated conversion result a-d register 0 convert input voltage at pin an 1 or compare input voltage at pin an 1 convert input voltage at pin an 0 or compare input voltage at pin an 0 comparison result an 0 pin comparator result bit conversion result a-d register 1 comparison result an 1 pin comparator result bit conversion result a-d register i comparison result an i pin comparator result bit
a-d converter 7906 group user s manual rev.2.0 12-28 12.10 repeat sweep mode 0 12.10 repeat sweep mode 0 in the repeat sweep mode, the a-d conversions for input voltages from multiple selected analog input pins are performed repeatedly. the a-d conversion is performed in ascending sequence from pin an 0 to pin an 7 . in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the a-d converter repeates its operation while the a-d conversion start bit = 1. 12.10.1 settings for repeat sweep mode 0 figures 12.10.1 and 12.10.2 show initial setting examples for related registers in the repeat sweep mode 0. fig. 12.10.1 initial setting example for related registers in repeat sweep mode 0 (1) selection of comparator function b7 b0 comparator function select register 0 (address dc 16 ) 0 : comparator is not selected. 1 : comparator is selected. an 0 an 1 an 2 an 3 an 4 a-d register i b7 b0 a-d register 0 (addresses 21 16, 20 16 ) a-d register 1 (addresses 23 16, 22 16 ) a-d register 2 (addresses 25 16, 24 16 ) a-d register 3 (addresses 27 16, 26 16 ) a-d register 4 (addresses 29 16, 28 16 ) when comparator function is selected when comparator function is not selected b7 b0 (b15) (b8) a value (comparison value) in the range from 00 16 through ff 16 is set. continued on figure 12.10.2. a-d control registers 0 and 1 b7 b0 a-d control register 0 (address 1e 16 ) 11 0 repeat sweep mode 0 x xx a-d conversion start bit 0 : a-d conversion halts. a-d conversion frequency ( ad ) select bit 0 see table 12.2.1. a-d sweep pin select bits b1 b0 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 4 (5 pins) b7 a-d control register 1 (address 1f 16 ) b0 0 resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode a-d conversion frequency ( ad ) select bit 1 see table 12.2.1. 0 v ref connection select bit 0 : pin v ref is connected. x : it may be either 0 or 1. 0 000 0
a-d converter 7906 group user s manual rev.2.0 12-29 fig. 12.10.2 initial setting example for related registers in repeat sweep mode 0 (2) 12.10 repeat sweep mode 0 operation starts. trigger generated setting of a-d conversion start bit to 1. b7 b0 a-d control register 0 (address 1e 16 ) a-d conversion start bit 1 port p7 direction register b7 b0 port p7 direction register (address 11 16 ) clear the bits, corresponding to the selected analog input pins, to 0. an 0 an 1 an 2 an 3 an 4 continued from preceding figure 12.10.1 note: writing to the following must be performed while the a-d converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the a-d converter. each bit of the a-d control register 0, except bit 6 each bit of the a-d control register 1 a-d register i (when the comparator function is selected) comparator function select register 0 especially, when the v ref connection select bit is cleared from 1 to 0, an interval of 1 s or more must be elapsed before occurrence of a trigger.
a-d converter 7906 group user s manual rev.2.0 12-30 12.10 repeat sweep mode 0 12.10.2 repeat sweep mode 0 operation ? the a-d converter starts its operation for the input voltage at pin an 0 when the a-d conversion start bit is set to 1. ? the a-d conversion for the input voltage at pin an 0 is completed after 49 cycles of ad in the 8- bit resolution mode, or 59 cycles of ad in the 10-bit resolution mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. when the comparator function is selected, the comparison for pin an 0 is completed after 14 cycles of ad . then, the result of the comparison is stored into the an 0 pin comparator result bit. ? the operations for all selected analog input pins are performed. the conversion result is transferred to the correponding a-d register i each time when the a-d conversion per one pin is completed. when the comparator function is selected, the comparison result is stored into the an i pin comparator result bit each time the comparison for one pin is completed. ? the operations for all selected analog input pins are performed again. ? the a-d converter repeates its operation until the a-d conversion start bit is cleared to 0 by software. note that the operation time for pins an 0 to an 4 is equivalent to the time for 6 pins when the a-d sweep pin select bits (bits 1, 0 at address 1f 16 ) = 10 2 . figure 12.10.3 shows the operation in the repeat sweep mode 0. fig. 12.10.3 operation in repeat sweep mode 0 convert input voltage at pin an i or compare input voltage at pin an i trigger generated conversion result a-d register 0 convert input voltage at pin an 1 or compare input voltage at pin an 1 convert input voltage at pin an 0 or compare input voltage at pin an 0 comparison result an 0 pin comparator result bit conversion result a-d register 1 comparison result an 1 pin comparator result bit conversion result a-d register i comparison result an i pin comparator result bit
a-d converter 7906 group user s manual rev.2.0 12-31 [precautions for a-d converter] [precautions for a-d converter] 1. be sure to clear the v ref connection select bit to 0. 2. writing to the following must be performed before a trigger is generated (in other words, while the a-d converter halts); this must be done independent of the operation mode of the a-d converter. each bit of the a-d control register 0, except bit 6 each bit of the a-d control register 1 a-d register i (when the comparator function is selected) comparator function select register 0 comparator result register 0 especially, when any instruction which clears the v ref connection select bit from 1 to 0 has been executed (in other words, the resistor ladder network is connected with pin v ref by this instruction), an interval of 1 s or more must be elapsed before occurrence of a trigger. 3. reading from a-d register i (when the comparator function is selected) must be performed before occurrence of a trigger (in other words, while the a-d converter halts.). the value undefined at reading. 4. when using pin an 3 , be sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). when using pin an 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 5. note that the operation time for pins an 0 to an 4 is equivalent to the time for 6 pins when the a-d sweep pin select bits (bits 1, 0 at address 1f 16 ) = 10 2 in the single sweep mode and repeat sweep mode 0. 6. refer to section appendix. 7 countermeasures against noise when using the a-d converter.
a-d converter 7906 group user s manual rev.2.0 12-32 [precautions for a-d converter] memorandum
chapter 13 d-a converter 13.1 overview 13.2 block description 13.3 d-a conversion method 13.4 setting method 13.5 operation description [precautions for d-a converter]
d-a converter 7906 group user? manual rev.2.0 13-2 13.1 overview, 13.2 block description 13.1 overview the m37906 is provided with two independent d-a converters of the r-2r type with 8-bit resolution. these d-a converters convert the values loaded in d-a register i (i = 0, 1) to analog voltages and output them from pin da i . 13.2 block description figure 13.2.1 shows the block diagram of the d-a converter. the registers related to the d-a converter are described below. data bus av ss r-2r ladder network d-a register i (i = 0, 1) (addresses 98 16 , 99 16 ) da i d-a i output enable bit v ref fig. 13.2.1 d-a converter block diagram
d-a converter 7906 group user s manual rev.2.0 13-3 13.2 block description 13.2.1 d-a control register figure 13.2.2 shows the structure of the d-a control register. pin da i (i = 0, 1) serves as the analog voltage output pin of the d-a converter. since pin da i is equipped with no internal buffer amplifier, it is necessary to connect a buffer amplifier externally to pin da i , if this pin is needed to be connected with a low-impedance load. pin da i is multiplexed with an analog input pin, external interrupt input pin, and trigger input pin in the pulse output port mode. when any of the d-a i output enable bits is set to 1 (output enabled), the corresponding pin is used only as pin da i , not as any other multiplexed input/output pin (including a programmable i/o port pin). fig. 13.2.2 structure of d-a control register (1) d-a i output enable bits (bits 0, 1) setting any of the d-a i output enable bits to 1 (output enabled) allows the corresponding pin da i to output d-a converted analog voltage, regardless of the contents of the corresponding bits of the port p7 direction register. 13.2.2 d-a register i (i = 0, 1) each pin da i outputs the analog voltage corresponding to the value loaded in d-a register i. figure 13.2.3 shows the structure of d-a register i. 0 1 7 to 2 bit name bit function at reset r/w d-a 0 output enable bit d-a 1 output enable bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 0: output is disabled. 1: output is enabled. (notes 1, 2) 0: output is disabled. 1: output is enabled. (notes 1, 2) 0 0 rw rw d-a control register (address 96 16 ) notes 1: pin da i is multiplexed with an analog input pin, external interrupt input pin, and trigger input pin in the pulse output port mode. when a d-a i output enable bit = 1 (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/output pin (including a programmable i/o port pin). 2: when not using the d-a converter, be sure to clear this bit to 0. 0 7 to 0 bit d-a register i (i = 0, 1) (addresses 98 16 , 99 16 ) function at reset r/w any value in the range from 00 16 through ff 16 can be set (note) , and this value will be d-a converted and will be output. rw b0 b7 fig. 13.2.3 structure of d-a register i undefined note: when not using the d-a converter, be sure to clear the contents of these bits to 00 16 .
d-a converter 7906 group user s manual rev.2.0 13-4 13.3 d-a conversion method 13.3 d-a conversion method the reference voltage v ref is divided according to the value loaded in d-a register i, and it is output as an analog voltage from pin da i . figure 13.3.1 shows the equivalent circuit diagram of the d-a converter. 2r rrrrr rr 2r 2r 2r 2r 2r 2r 2r 2r lsb msb av ss v ref d-a register i d-a i output enable bit da i 0 1 01 note: in this case, the value of d-a register i is 2a 16 . fig. 13.3.1 equivalent circuit diagram of d-a converter
d-a converter 7906 group user s manual rev.2.0 13-5 13.4 setting method figure 13.4.1 shows an initial setting example of registers related to the d-a converter. fig. 13.4.1 initial setting example of registers related to d-a converter 13.5 operation description when any of the d-a i output enable bits is set to 1, the value loaded in d-a register i is converted to an analog voltage, and the analog voltage is output from pin da i . the relationship between analog output voltage v and value n, which has been loaded in d-a register i, can be expressed as follows : v = v ref ? (n = 0 to 255) v ref : reference voltage 13.4 setting method, 13.5 operation description analog voltage output started setting of the d-a i output enable bit to 1 . b7 b0 d-a control register (address 96 16 ) d-a 0 output enable bit d-a 1 output enable bit setting of a value to d-a register i b7 b0 d-a register 0 (address 98 16 ) d-a register 1 (address 99 16 ) a value (00 16 to ff 16 ) to be d-a converted is set . n 256
d-a converter 7906 group user s manual rev.2.0 13-6 [precautions for d-a converter] [precautions for d-a converter] 1. pin da i is multiplexed with an analog input pin, external interrupt input pin, and trigger input pin in the pulse output port mode. when any of the d-a i output enable bits is set to 1 (output enabled), the corresponding pin is used as pin da i , not as any other multiplexed input/output pin (including a programmable i/o port pin). 2. when not using the d-a converter, be sure to do as follows: clear the d-a i (i = 0, 1) output enable bit (bits 0, 1 at address 96 16 ) to 0. clear the contents of d-a register i (addresses 98 16 , 99 16 ) to 00 16 .
chapter 14 watchdog timer 14.1 block description 14.2 operation description [precautions for watchdog timer]
watchdog timer 7906 group user? manual rev.2.0 14-2 14.1 block description the watchdog timer functions as follows: detects a program runaway. at stop mode termination, measures a certain time after oscillation starts. (refer to section ?5.3 stop mode. ) 14.1 block description figure 14.1.1 shows the block diagram of the watchdog timer, and registers relevant to the watchdog timer are described below. 1/ 16 wf 32 wf 512 f 2 1/ 16 1 0 rese t fx 16 fx 32 fx 64 fx 12 8 wait mode divided f(x in ) watchdog timer clock source select bits at stp termination watchdog timer register: address 60 16 watchdog timer frequency select bit: bit 0 at address 61 16 watchdog timer clock source select bits at stp termination: bits 7, 6 at address 61 16 ? when the most significant bit of the watchdog timer becomes 0, this signal will be generated. note: during the stop mode and until the stop mode is terminated, setting for disabling the watchdog timer is ignored. (refer to section 14.1.3 particular function select register 2. ) stp instruction writing to watchdog timer register disables watchdog timer (note) . watchdog timer frequency select bit stop mode watchdog timer fff 16 is set. ? watchdog timer interrupt request fig. 14.1.1 block diagram of watchdog timer
watchdog timer 7906 group user s manual rev.2.0 14-3 14.1.1 watchdog timer figure 14.1.2 shows the structure of the watchdog timer register. the watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 61 16 ) is counted down. a value of fff 16 is automatically set in the watchdog timer if any of the following conditions is satisfied. an arbitrary value cannot be set to the watchdog timer. when dummy data is written to the watchdog timer register. (see figure 14.1.2.) when the most significant bit of watchdog timer becomes 0. when the stp instruction is executed. (refer to section 15.3 stop mode. ) at reset 14.1 block description fig. 14.1.2 structure of watchdog timer register fig. 14.1.3 structure of watchdog timer frequency select register 14.1.2 watchdog timer frequency select register figure 14.1.3 shows the structure of the watchdog timer frequency select register. undefined 7 to 0 initializes the watchdog timer. when dummy data has been written to this register, the watchdog timer s value is initialized to fff 16 (dummy data: 00 16 to ff 16 ). b0 b7 watchdog timer register (address 60 16 ) bit function at reset r/w rw rw rw bit name bit 0 5 to 1 6 7 watchdog timer frequency select register (address 61 16 ) function at reset r/w watchdog timer frequency select bit nothing is assigned. watchdog timer clock source select bits at stp termination 0 undefined 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 : wf 512 1 : wf 32 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 b7 b6 (1) watchdog timer frequency select bit (bit 0) this bit is used to select a count source of the watchdog timer. (2) watchdog timer clock source select bits at stp termination (bits 7, 6) these bits are used to select a count source at stop mode termination. for details of the operation at stop mode termination, refer to section 15.3 stop mode.
watchdog timer 7906 group user s manual rev.2.0 14-4 14.1 block description 14.1.3 particular function select register 2 when not using the watchdog timer, this register can be used to disable the watchdog timer. figure 14.1.4 shows the structure of the particular function select register 2. fig. 14.1.4 structure of particular function select register 2 in addition, even when the watchdog timer is disabled by this register, the watchdog timer can be active only at the stop mode termination if the external clock input select bit (bit 1 at address 62 16 ) = 0. (refer to section 15.3 stop mode. ) undefined 7 to 0 bit function at reset r/w disables the watchdog timer. when values of 79 16 and 50 16 succeedingly in this order, the watchdog timer will stop its operation. b0 b7 particular function select register 2 (address 64 16 ) note: after reset, this register can be set only once. writing to this register requires the following procedure: write values of 79 16 and 50 16 to this register succeedingly in this order. for the above writing, be sure to use the movmb ( movm when m = 1) instruction or the stab ( sta when m = 1). note that the following: if an interrupt occurs between writing of 79 16 and next writing of 50 16, the watchdog timer does not stop its operation. if any of the following has been performed after reset, writing to this register is disabled from that time: if this register is read out. if writing to this register is performed by the procedure other than the above procedure.
watchdog timer 7906 group user s manual rev.2.0 14-5 14.2 operation description 14.2 operation description the operations of the watchdog timer are described below. 14.2.1 basic operation ? watchdog timer starts counting down from fff 16 . ? when the watchdog timer s most significant bit becomes 0 (counted 2048 times), a watchdog timer interrupt request occurs. (see table 14.2.1.) ? when the interrupt request occurs in above ? , a value of fff 16 is set to the watchdog timer. a watchdog timer interrupt is a non-maskable interrupt. when a watchdog timer interrupt request is accepted, the processor interrupt priority level (ipl) is set to 111 2 . table 14.2.1 occurrence interval of watchdog timer interrupt request f(f sys ) = 20 mhz occurrence interval (note) 52.43 ms 3.28 ms count source wf 512 wf 32 watchdog timer frequency select bit 0 1 note: this applies when the peripheral device s clock select bits 1, 0 (bits 7, 6 at address bc 16 ) = 00 2 .
watchdog timer 7906 group user s manual rev.2.0 14-6 be sure to write dummy data to the watchdog timer register (address 60 16 ) before the most significant bit of the watchdog timer becomes 0. when writing to the watchdog timer is not performed owing to a program runaway and the watchdog timer s most significant bit becomes 0, a watchdog timer interrupt request occurs. this informs that a program runaway has occurred. in order to reset the microcomputer when a program runaway has been detected, write 1 to the software reset bit (bit 6 at address 5e 16 ) in the watchdog timer interrupt routine. figure 14.2.1 shows an example of a program runaway detected by the watchdog timer. 14.2 operation description rti main routine watchdog timer interrupt routine watchdog timer register (address 60 16 ) 8-bit dummy data watchdog timer interrupt request occurrence (in other words, program run- away is detected.) watchdog timer initialized (value of watchdog timer : fff 16 ) ( note 1 ) software reset bit (bit 6 at address 5e 16 ) 1 ( note 2 ) reset microcomputer notes 1: be sure to initialize the watchdog timer before the most significant bit of the watchdog timer becomes 0. (in other words, be sure to write dummy data to address 60 16 before a watchdog timer interrupt request occurs). 2: when a program runaway occurs, values of the data bank register (dt), direct page register (dpri), etc., may be changed. when 1 is written to the software reset bit by an addressing mode using dt, dpri, etc., be sure to set values to dt and dpri, etc. again. fig. 14.2.1 example of program runaway detection by watchdog timer
watchdog timer 7906 group user s manual rev.2.0 14-7 14.2.2 stop period the watchdog timer stops its operation in any of the following cases: ? during wait mode (refer to section 15.4 wait mode. ) ? during stop mode (refer to section 15.3 stop mode. ) when state ? has been terminated, the watchdog timer restarts counting from the state immediately before it stops its operation. for the watchdog timer s operation at termination of state ? , refer to section 14.2.3 operation in stop mode. 14.2.3 operations in stop mode when the stp instruction has been executed, a value of fff 16 is set to the watchdog timer, and the watchdog timer stops its operation in the stop mode. immediately after the stop mode termination, the watchdog timer operates as follows. (1) when stop mode is terminated by hardware reset supply of cpu and biu starts immediately after the stop mode termination, and the microcomputer performs operation after reset. (refer to chapter 3. reset. ) the watchdog timer frequency select bit becomes 0, and the watchdog timer starts counting of wf 512 from fff 16 . (2) when stop mode is terminated by interrupt occurrence (with watchdog timer used) (note) immediately after the stop mode termination, the watchdog timer starts counting the count source selected by the watchdog timer clock source select bits at stp termination (bits 6, 7 at address 61 16 ), starting from fff 16 . it is independent of the watchdog timer frequency select bit (bit 0 at address 61 16 ). when the most significant bit of the watchdog timer becomes 0, supply of cpu and biu starts. ( at this time, no watchdog timer interrupt request occurs.) when supply of cpu and biu starts, the routine of the interrupt which the microcomputer used to terminate the stop mode is executed. the watchdog timer restarts counting of the count source (wf 32 or wf 512 ), which was counted immediately before execution of the stp instruction, starting from fff 16 . note: for the setting of the usage of the watchdog timer, refer to section 15.3 stop mode. (3) when stop mode is terminated by interrupt occurrence (with watchdog timer not used) (note) supply of cpu and biu starts immediately after the stop mode termination, and the routine of the interrupt which the microcomputer used to terminate the stop mode is executed. the watchdog timer restarts counting of the count source (wf 32 or wf 512 ), which was counted immediately before execution of the stp instruction, starting from fff 16 . note: for the setting of the usage of the watchdog timer, refer to section 15.3 stop mode. 14.2 operation description
watchdog timer 7906 group user s manual rev.2.0 14-8 [precautions for watchdog timer] [precautions for watchdog timer] 1. when dummy data has been written to address 60 16 with the 16-bit data length, writing to address 61 16 is simultaneously performed. accordingly, when the user does not want to change the contents of the watchdog timer frequency select bit (bit 0 at address 61 16 ) and watchdog timer clock source select bits at stp termination (bits 6, 7 at address 61 16 ), be sure to write again the values which are currently set in these bits, simultaneously with writing to address 60 16 . 2. when the stp instruction is executed, the watchdog timer stops its operation. if the stp instruction s code (31 16 , 30 16 ) has accidentally been executed owing to a program runaway, the watchdog timer stops its operation. therefore, in the system where the watchdog timer is used to detect a program runaway, we recommend that the stp instruction invalidity select bit (bit 0 at address 62 16 ) = 1. ( stp instruction is invalid.) refer to section 15.3 stop mode.
chapter 15 stop and wait modes 15.1 overview 15.2 block description 15.3 stop mode 15.4 wait mode
stop and wait modes 7906 group user? manual rev.2.0 15-2 15.1 overview 15.1 overview when there is no need for operation of the central processing unit (cpu), the stop and wait modes are used to stop oscillation or internal clock. as a result, the power consumption can be saved. the microcomputer enters the stop mode when the stp instruction has been executed; the microcomputer enters the wait mode when the wit instruction has been executed. the stop and wait modes are terminated by an interrupt request occurrence or hardware reset. table 15.1.1 lists the states in the stop and wait modes and operations after these modes are terminated. table 15.1.1 states in stop and wait modes and operations after these modes are terminated active. operates (note 1). inactive. active. inactive. operates. operates. operates. operates. stopped. retains the state at the wit instruction execution . inactive. can operate only in the event counter mode. can operate only when an external clock is selected. stopped. stopped. internal peripheral when watchdog timer is used at termination (see figure 15.3.1.) stop mode operation after hardware reset inactive. stopped. inactive. inactive. inactive. can operate only in the event counter mode. can operate only when an external clock is selected. stopped. stopped. stopped. retains the state at the stp instruction execution. timers a, b serial i/o a-d converter d-a converter watchdog timer pins states supply of cpu , biu starts after a certain time has been measured by using the watchdog timer. oscillation pll frequency multiplier cpu , biu f sys , clock 1 , f 1 to f 4096 wf 32 , wf 512 operation after termination when watchdog timer is not used at termination (see figure 15.3.1.) wait mode system clock is active. (bit 3 at address 63 16 = ?? system clock is inactive. (bit 3 at address 63 16 = ?? supply of cpu , biu starts immediately after termi- nation (note 2) . operation after hardware reset supply of cpu , biu starts immediately after termination. notes 1: this applies when the pll circuit operation enable bit (bit 1 at address bc 16 ) = ?. 2: see table 15.3.2. item termination due to interrupt request occurrence termination due to hardware reset
stop and wait modes 7906 group user? manual rev.2.0 15-3 15.2 block description 15.2 block description figure 15.2.1 shows the block diagram of the clock generating circuit with the stp and wit instructions. also, registers relevant to these modes are described below. fig. 15.2.1 block diagram of clock generating circuit with stp and wit instructions f 2 f 64 f 512 f 4096 q r s stp instruction biu (clock for biu) cpu (clock for cpu) cpu wait request 1/4 1/8 1/8 reset watchdog timer frequency select bit : bit 0 at address 61 16 watchdog timer clock source select bits at stp termination : bits 6, 7 at address 61 16 external clock input select bit : bit 1 at address 62 16 system clock stop select bit at wit : bit 3 at address 63 16 pll circuit operation enable bit : bit 1 at address bc 16 pll multiplication ratio select bits : bits 2, 3 at address bc 16 system clock select bit : bit 5 at address bc 16 peripheral device s clock select bits 0, 1 : bits 6, 7 at address bc 16 1/8 1/2 1/16 watchdog timer wf 32 wf 512 f 16 f 1 peripheral device s clocks 0 1 watchdog timer frequency select bit x in x out system clock stop select bit at wit 1/16 0 1 watchdog timer clock source select bits at stp termination 1 wait mode 1 0 1 0 1/2 1 0 1 wait mode system clock select bit pll frequency multiplier f pll v cont wait mode external clock input select bit q r s stp instruction interrupt request q r s wit instruction interrupt request wait mode pll circuit operation enable bit pll multiplication ratio select bits fx in f/n 0 fx 16 fx 32 fx 64 fx 128 fx 16 fx 32 fx 64 fx 128 peripheral device s clock select bit 0 peripheral device s clock select bit 1 biu : bus interface unit cpu : central processing unit ? : signal generated when the watchdog timer s most significant bit becomes 0. f sys system clock frequency select bit ? operating clock for serial i/o, timer b a-d conversion frequency ( ad ) clock source operating clock for timer a external clock input select bit interrupt request
stop and wait modes 7906 group user s manual rev.2.0 15-4 15.2 block description 15.2.1 particular function select register 0 figure 15.2.2 shows the structure of the particular function select register 0, and figure 15.2.3 shows the writing procedure for the particular function select register 0. (1) stp instruction invalidity select bit (bit 0) setting this bit to 1 invalidates the stp instruction. when using the stop mode, be sure to clear this bit to 0. writing to this bit requires the following procedure: write 55 16 to address 62 16 . succeedingly, write 0 or 1 to this bit. (see figure 15.2.3.) if an interrupt occurs between writing of 55 16 and next writing of 0 or 1, latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bit s contents after writing of 0 or 1, and verify whether 0 or 1 has correctly been written or not. rw (note) rw (note) rw 0 0 0 bit name bit particular function select register 0 (address 62 16 ) function at reset r/w stp instruction invalidity select bit external clcok input select bit fix these bits to 000000. b7 b6 b5 b4 b3 b2 b1 b0 0 : stp instruction is valid. 1 : stp instruction is invalid. 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = 0, watchdog timer is not used at stop mode termination. when the system clock select bit = 1, watchdog timer is used at stop mode termination. 00 0 00 0 fig. 15.2.2 structure of particular function select register 0 note: writing to these bits requires the following procedure: write 55 16 to this register. (the bit status does not change only by this writing.) succeedingly, write 0 or 1 to each bit. also, use the movmb ( movm when m = 1) instruction or stab ( sta when m = 1) instruction. if an interrupt occurs between writing of 55 16 and next writing of 0 or 1, latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bit s contents after writing of 0 or 1, and verify whether 0 or 1 has correctly been written or not. 0 1 7 to 2
stop and wait modes 7906 group user s manual rev.2.0 15-5 15.2 block description (2) external clock input select bit (bit 1) when this bit = 0, the oscillation driver circuit between pins x in and x out is operationg. at the stop mode termination owing to an interrupt occurrence, the watchdog timer is used. setting this bit to 1 stops the oscillation driver circuit between pins x in and x out and keeps the output level at pin x out being h. (refer to section ?6.3 stop of oscillation circuit. ) at the stop mode termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address bc 16 ) = 0, where as the watchdog timer is used if the system clock select bit = 1. to rewrite this bit, write 0 or 1 just after writing of 55 16 to address 62 16 . (see figure 15.2.3.) note that if an interrupt occurs between writing of 55 16 and next writing of 0 or 1, latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bit s contents after writing of 0 or 1, and verify whether 0 or 1 has correctly been written or not. in addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16 ), the watchdog timer can be active only at the stop mode termination if this bit = 0. (refer to section ?5.3 stop mode. ) fig. 15.2.3 writing procedure for particular function select register 0 00 0 writing of 55 16 b0 particular function select register 0 (address 62 16 ) b7 1 setting completed 1 0 writing to bits 0, 1 b0 particular function select register 0 (address 62 16 ) b7 external clock input select bit 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = 0, watchdog timer is not used at stop mode termination. when the system clock select bit = 1, watchdog timer is used at stop mode termination. stp instruction invalidity select bit 0 : stp instruction is valid. 1 : stp instruction is invalid. next instructio n note: bits state does not change only by writing of 55 16 . 00 0 00 0 1 1 0 0
stop and wait modes 7906 group user s manual rev.2.0 15-6 15.2 block description 15.2.2 particular function select register 1 figure 15.2.4 shows the structure of the particular function select register 1. notes 1: at power-on rest, this bit becomes 0. at hardware reset or software reset, this bit retains the value just before reset. 2: even when 1 is written, the bit status will not change. 3: setting this bit to 1 must be performed just before execution of the wit instruction. also, after the wait state is terminated, this bit must be cleared to 0 immediately. (note 1) (note 1) 0 0 0 0 0 0 bit name bit particular function select register 1 ( address 63 16 ) function at reset r/w stp-instruction-execution status bit wit-instruction-execution status bit fix this bit to 0 . system clock stop select bit at wit (note 3) fix this bit to 0 . the value is 0 at reading. timer b2 clock source select bit (valid in event counter mode) the value is 0 at reading. b7 b6 b5 b4 b3 b2 b1 b0 0 : normal operation. 1 : stp instruction has been executed. 0 : normal operation. 1 : wit instruction has been executed. 0 : in wait mode, system clock f sys is active. 1 : in wait mode, system clock f sys is stopped. 0 : external signal input to the tb2 in pin is counted. 1 : fx 32 is counted. rw (note 2) rw (note 2) rw rw rw rw fig. 15.2.4 structure of particular function select register 1 0 1 2 3 4 5 6 7 (1) stp-instruction-execution status bit (bit 0) when the microcomputer enters the stop mode, this bit becomes 1, indicating that the stp instruction has been executed. this bit becomes 0 at power-on reset. at hardware reset and software reset, this bit retains the value immediately before reset. therefore, this bit is used for the following verification: which of the power-on reset and hardware reset has been used to reset the system? has the hardware reset been used for the stop mode termination? this bit is cleared to 0 by writing 0 to this bit. although, even when 1 is written to this bit, this bit does not change. at the stop mode termination, be sure to clear this bit to 0 by software. (2) wit-instruction-execution status bit (bit 1) when the microcomputer enters the wait mode, this bit becomes 1, indicating that the wit instruction has been executed. this bit becomes 0 at power-on reset. at hardware reset and software reset, this bit retains the value immediately before reset. therefore, this bit is used for the following verification: which of the power-on reset and hardware reset has been used to reset the system? has the hardware reset been used for the wait mode termination? this bit is cleared to 0 by writing 0 to this bit. although, even when 1 is written to this bit, this bit does not change. at the wait mode termination, be sure to clear this bit to 0 by software. 00
stop and wait modes 7906 group user s manual rev.2.0 15-7 15.2 block description fig. 15.2.5 structure of watchdog timer frequency select register 15.2.3 watchdog timer frequency select register figure 15.2.5 shows the structure of the watchdog timer frequency select register. rw rw rw bit name bit 0 5 to 1 6 7 watchdog timer frequency select register (address 61 16 ) function at reset r/w watchdog timer frequency select bit nothing is assigned. watchdog timer clock source select bits at stp termination 0 undefined 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 : wf 512 1 : wf 32 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 b7 b6 (1) watchdog timer clock source select bits at stp termination (bits 7, 6) these bits are used to select a count source at stop mode termination. for details of the operation at stop mode termination, refer to section 15.3 stop mode.
stop and wait modes 7906 group user s manual rev.2.0 15-8 15.3 stop mode 15.3 stop mode when the stp instruction has been executed, each of the oscillation and the pll frequency multiplier s operation becomes inactive. this state is called stop mode. (see table 15.1.1) in the stop mode, even when oscillation becomes inactive, the contents of the internal ram can be retained if vcc (the power source voltage) v ram (ram hold voltage). furthermore, since the cpu and internal peripheral devices which use any of clocks f 1 to f 4096 , wf 32 , wf 512 stop their operations, the power consumption can be saved. the stop mode is terminated owing to an interrupt request occurrence or hardware reset. when terminated owing to an interrupt request occurrence, an instruction can be executed immediately after termination if all of the following conditions are satisfied. (refer to section 15.3.2 terminate operation at interrupt request occurrence (when not using watchdog timer). ) : an stable clock is input from the external. (the external clock input select bit (bit 1 at address 62 16 ) = 1. ) the pll frequency multiplier is not used. (the system clock select bit (bit 5 at address bc 16 ) = 0. ) when terminated owing to an interrupt request occurrence, an instruction will be executed after the oscillation stabilizing time has been measured by using the watchdog timer if any of the following conditions is satisfied. (refer to section 15.3.1 terminate operation at interrupt request occurrence (when using watchdog timer). ) : an oscillator is used. (the external clock input select bit (bit 1 at address 62 16 ) = 0. ) the pll frequency multiplier is used. (the system clock select bit (bit 5 at address bc 16 ) = 1. ) 15.3.1 terminate operation at interrupt request occurrence (when using watchdog timer) at the stop mode termination, execution of an instruction is started after a certain time has been measured by using the watchdog timer. (see figure 15.3.1.) ? when an interrupt request occurs, an oscillator starts its operation. also, when the pll circuit operation enable bit (bit 1 at address bc 16 ) = 1, the pll frequency multiplier starts its operation. simultaneously with this, each supply of clocks f sys , 1 , f 1 to f 4096 , wf 32 , wf 512 starts. ? by start of oscillation in ? , the watchdog timer starts its operation. regardless of the watchdog timer frequency select bit (bit 0 at address 61 16 ), the watchdog timer counts a count source (fx 16 to fx 128 ), which is selected by the watchdog timer clock source select bits at stp termination (bits 7, 6 at address 61 16 ). this counting is started from a value of fff 16 . ? when the most significant bit (msb) of the watchdog timer becomes 0, each supply of cpu , biu starts. (at this time, no watchdog timer interrupt request occurs.) also, the count source of the watchdog timer returns to the count source selected by the watchdog timer frequency select bits (in order words, wf 32 or wf 512 ). ? the interrupt request which occurred in ? is accepted. for the watchdog timer, refer to chapter 14. watchdog timer. table 15.3.1 lists the interrupts which can be used to terminate the stop mode. table 15.3.1 interrupts which can be used to terminate stop mode usage condition for interrupt request occurrence in event counter mode when an external clock is selected. interrupt int i interrupt (i = 3 to 7) timer ai interrupt (i = 0 to 2, 4, 9) timer bi interrupt (i = 0 to 2) uarti transmit interrupt (i = 0, 1) uarti receive interrupt (i = 0, 1) notes 1: when multiple interrupts are enabled, the stop mode is terminated owing to the interrupt request which occurs first. 2: for interrupts, refer to chapter 6. interrupts and each peripheral device s chapter.
stop and wait modes 7906 group user s manual rev.2.0 15-9 15.3 stop mode before executing the stp instruction, be sure to enable an interrupt which is to be used for the stop mode termination. also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination, is higher than the processor interrupt priority level (ipl) of a routine where the stp instruction is executed. after oscillation starts ( ? ), there is a possibility that each interrupt request occurs until the supply of cpu , biu starts ( ? ). the interrupt requests which occurred during this period are accepted in order of priority after the watchdog timer s msb becomes 0. (when the level sense of an int i interrupt is used, however, no interrupt request is retained. therefore, if pin int i is at the invalid level when the watchdog timer s msb becomes 0, no interrupt request is accepted.) for an interrupt which has no need to be accepted, be sure to set its interrupt priority level to 0 (interrupt disabled) before executing the stp instruction. 15.3.2 terminate operation at interrupt request occurrence (when not using watchdog timer) at the stop mode termination, an instruction is executed without use of the watchdog timer. (see figure 15.3.1.) ? when an interrupt request occurs, clock input from pin x in starts. simultaneously, supply of clocks f sys , 1 , f 1 to f 4096 , wf 32 , wf 512 starts. ? supply of cpu , biu starts after the time listed in table 15.3.2 has elapsed. ? the interrupt request which occurred in ? is accepted. watchdog timer clock source select bits at stp termination (bits 7, 6 at address 61 16 ) 00 01 10 11 fx in ? 19 cycles fx in ? 11 cycles fx in ? 67 cycles fx in ? 35 cycles time until supply of cpu and biu starts table 15.3.2 time after stop mode is terminated until supply of cpu , biu starts before executing the stp instruction, be sure to set as follows: enable an interrupt which is to be used for the stop mode termination. also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination, is higher than the processor interrupt priority level (ipl) of a routine where the stp instruction is executed. the external clock input select bit (bit 1 at address 62 16 ) = 1 (note) the system clock select bit (bit 5 at address bc 16 ) = 0 (note) note: simultaneously, the oscillation driver circuit between pins x in and x out stops, and the output level at pin x out is kept h. (refer to section 16.3 stop of oscillation circuit. )
stop and wait modes 7906 group user s manual rev.2.0 15-10 15.3 stop mode fig. 15.3.1 stop mode terminate sequence owing to interrupt request occurrence interrupt request to be used for termination occurs. clock input from pin x in starts. watchdog timer starts counting. stop mode biu fx in 1 operating stopped operating operating stopped operating cpu internal peripheral devices stp instru- ction is executed. value of watchdog timer 7ff 16 interrupt request to be used for stop mode termination (interrupt request bit) fff 16 each supply of cpu , biu starts. interrupt request which was used for termination is accepted. when not using watchdog timer (note) stopped operating note: time listed in table 15.3.2. see figure 19.1.3 for the built-in flash memory version. operating stopped stopped operating operating stopped operating operating cpu internal peripheral devices interrupt request to be used for termination occurs. oscillation starts. (when an external clock is input from pin x in , clock input starts.) pll frequency multiplier starts its operation. watchdog timer starts counting. value of watchdog timer 7ff 16 interrupt request to be used for stop mode termination (interrupt request bit) fff 16 watchdog timer s msb = 0 (however, watchdog timer interrupt request does not occur.) each supply of cpu , biu starts. interrupt request which was used for termination is accepted. stop mode biu fx in 1 stp instru- ction is executed. when using watchdog timer f pll fx i ? 2048 counts (note) note: this applies when the pll circuit operation enable bit (bit 1 at address bc 16 ) = 1. these are clocks selected by the watchdog timer clock source select bits at stp termination (bits 7, 6 at address 61 16 .) fx i : fx 16 , fx 32 , fx 64 , fx 128 .
stop and wait modes 7906 group user s manual rev.2.0 15-11 15.3 stop mode 15.3.3 terminate operation at hardware reset although each of the cpu and sfr area is initialized, the contents of the internal ram immediately before the stp instruction execution are retained. the terminate sequence is the same as the internal processing sequence after reset. for reset, refer to chapter 3. reset. also, the stp-instruction-execution status bit (bit 0 at address 63 16 ) is used for the following verification: which of the power-on reset and hardware reset has been used to reset the system? has the hardware reset been used for the stop mode termination?
stop and wait modes 7906 group user s manual rev.2.0 15-12 15.4 wait mode 15.4 wait mode when the wit instruction is executed, both of cpu and biu become inactive. (the oscillation does not become inactive.) this state is called wait mode. (see table 15.1.1.) in the wait mode, the power consumption can be saved with vcc (the power source voltage) retained. when using no internal peripheral device in the wait mode, the power consumption can be saved furthermore since each of f sys and internal peripheral device s operation clock can be inactive. (refer to section 16.2 stop of system clock in wait mode. ) the wait mode is terminated owing to an interrupt request occurrence or hardware reset. the wait mode terminate operation is described below. 15.4.1 terminate operation at interrupt request occurrence ? when an interrupt request occurs, each supply of cpu and biu starts. ? the interrupt request which occurred in ? is accepted. table 15.4.1 lists the interrupts which can be used for the wait mode termination. before executing the wit instruction, be sure to enable an interrupt which is to be used for the wait mode termination. also, make sure that the interrupt priority level of an interrupt, which is to be used for termination, is higher than the processor interrupt priority level (ipl) of a routine where the wit instruction is executed. also, when multiple interrupts in table 15.4.1 are enabled, the wait mode is terminated owing to the interrupt request which occurs first. 15.4.2 terminate operation at hardware reset although each of the cpu and sfr area is initialized, the contents of the internal ram immediately before the wit instruction execution are retained. the terminate sequence is the same as the internal processing sequence after reset. for reset, refer to chapter 3. reset. also, the wit-instruction-execution status bit (bit 1 at address 63 16 ) is used for the following verification: which of the power-on reset and hardware reset has been used to reset the system? has the hardware reset been used for the wait mode termination? table 15.4.1 interrupts which can be used for wait mode termination in event counter mode when an external clock is selected. do not use. int i interrupt (i = 3 to 7) timer ai interrupt (i = 0 to 2, 4, 9) timer bi interrupt (i = 0 to 2) uarti transmit interrupt (i = 0, 1) uarti receive interrupt (i = 0, 1) a-d conversion interrupt notes 1: when multiple interrupts are enabled, the wait mode is terminated owing to the interrupt request which occurs first. 2: for interrupts, refer to chapter 6. interrupts and each peripheral device s chapter. interrupt system clock in action usage conditions for interrupt request occurrences system clock out of action
chapter 16 power saving functions 16.1 overview 16.2 inactivity of system clock in wait mode 16.3 stop of oscillation circuit 16.4 pin v ref disconnection
power saving functions 7906 group user? manual rev.2.0 16-2 16.1 overview chapter 15. stop and wait modes chapter 4. clock generating circuit , section 15.3 stop mode chapter 12. a-d converter this chapter explains the functions to save the power consumption of the microcomputer and the total system including the microcomputer. 16.1 overview table 16.1.1 lists the overview of the power saving functions. each of these functions saves the power consumption of the total system. the registers related to the power saving functions are explained in the following. table 16.1.1 overview of power saving functions item inactivity of system clock in wait mode stop of oscillation circuit pin v ref disconnection in the wait mode, operating clocks for the internal peripheral devices and f sys can be inactive. when a stable clock externally generated is used, the drive circuit for oscillation between pins x in and x out can be stopped. (the output level at pin x out is fixed to ?.? the v ref input can be disconnected when the a-d converter is not used function reference
power saving functions 7906 group user? manual rev.2.0 16-3 16.1 overview rw (note) rw (note) rw 0 0 0 bit name bit 0 1 7 to 2 particular function select register 0 (address 62 16 ) function at reset r/w stp instruction invalidity select bit external clcok input select bit fix these bits to ?00000. b7 b6 b5 b4 b3 b2 b1 b0 0 : stp instruction is valid. 1 : stp instruction is invalid. 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = ?, watchdog timer is not used at stop mode termination. when the system clock select bit = ?, watchdog timer is used at stop mode termination. 00 0 00 0 16.1.1 particular function select register 0 figure 16.1.1 shows the structure of the particular function select register 0, and figure 16.1.2 shows the writing procedure for the particular function select register 0. fig. 16.1.1 structure of particular function select register 0 note: writing to these bits requires the following procedure: ?write ?5 16 ?to this register. (the bit status does not change only by this writing.) ?succeedingly, write ??or ??to each bit. also, use the movmb ( movm when m = 1) instruction or stab ( sta when m = 1) instruction. if an interrupt occurs between writing of ?5 16 ?and next writing of ??or ?,?latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bits contents after writing of ??or ?,?and verify whether ??or ??has correctly been written or not.
power saving functions 7906 group user? manual rev.2.0 16-4 16.1 overview fig. 16.1.2 writing procedure for particular function select register 0 (1) external clock input select bit (bit 1) when this bit = ?,?the oscillation driver circuit between pins x in and x out is operationg. also, at the stop mode termination owing to an interrupt request occurrence, the watchdog timer is used. setting this bit to ??stops the oscillation driver circuit between pins x in and x out and keeps the output level at pin x out being ?.?(refer to section ?6.3 stop of oscillation circuit. ) at the stop mode termination owing to an interrupt request occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address bc 16 ) = ?,?where as the watchdog timer is used if the system clock select bit = ?. to rewrite this bit, write ??or ??just after writing of ?5 16 ?to address 62 16 . (see figure 16.1.2.) note that if an interrupt occurs between writing of ?5 16 ?and next writing of ??or ?,?latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bit? contents after writing of ??or ?,?and verify whether ??or ??has correctly been written or not. in addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16 ), the watchdog timer can be active only at the stop mode termination if this bit = ?. (refer to section ?5.3 stop mode. ) 00 0 writing of 55 16 b0 particular function select register 0 (address 62 16 ) b7 1 setting completed 1 0 writing to bits 0, 1 b0 particular function select register 0 (address 62 16 ) b7 external clock input select bit 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = 0, watchdog timer is not used at stop mode termination. when the system clock select bit = 1, watchdog timer is used at stop mode termination. stp instruction invalidity select bit 0 : stp instruction is valid. 1 : stp instruction is invalid. next instructio n note: bits state does not change only by writing of 55 16 . 00 0 00 0 1 1 0 0
power saving functions 7906 group user s manual rev.2.0 16-5 16.1.2 particular function select register 1 figure 16.1.3 shows the structure of the particular function select register 1. fig. 16.1.3 structure of particular function select register 1 (1) system clock stop select bit at wit (bit 3) setting this bit to 1 makes the following clocks inactive in the wait mode: the operating clocks for the internal peripheral devices and f sys . (refer to section 16.2 inactivity of system clock in wait mode. ) 16.1 overview 0 1 2 3 4 5 6 7 rw (note 2) rw (note 2) rw rw rw rw notes 1: at power-on reset, this bit becomes 0. at hardware reset or software reset, this bit retains the value just before reset. 2: even when 1 is written, the bit status will not change. 3: setting this bit to 1 must be performed just before execution of the wit instruction. also, after the wait state is termi- nated, this bit must be cleared to 0 immediately. (note 1) (note 1) 0 0 0 0 0 0 particular function select register 1 (address 63 16 ) b7 b6 b5 b4 b3 b2 b1 b0 bit name bit function at reset r/w stp-instruction-execution status bit wit-instruction-execution status bit fix this bit to 0. system clock stop select bit at wit (note 3) fix this bit to 0. the value is 0 at reading. timer b2 clock source select bit (valid in event counter mode.) the value is 0 at reading. 0 : normal operation. 1 : during execution of stp instruction 0 : normal operation. 1 : during execution of wit instruction 0 : external signal input to the tb2 in pin is counted. 1 : fx 32 is counted. 0 : in the wait mode, system clock f sys is active. 1 : in the wait mode, system clock f sys is inactive. 00
power saving functions 7906 group user s manual rev.2.0 16-6 operation after termination 16.2 inactivity of system clock in wait mode 16.2 inactivity of system clock in wait mode in the wait mode, if there is not need to operate the internal peripheral devices, setting the system clock stop select bit at wit (see figure 16.1.3.) to 1 makes the following clocks inactive: the operating clocks for the internal peripheral devices and f sys . this saves the power consumption of the microcomputer. table 16.2.1 lists the states and operations in the wait mode and after this mode is terminated. table 16.2.1 states and operations in wait mode and after this mode is terminated active. operates (note) . inactive. active. inactive. operates. operates. operates. operates. stopped. retains the state at the wit instruction execution. system clock is inactive. (bit 3 at address 63 16 = 1) inactive. can operate only in the event counter mode. can operate only when an external clock is selected. stopped. stopped. item termination due to interrupt request occurrence timers a, b serial i/o a-d converter d-a converter watchdog timer pins states oscillation pll frequency multiplier cpu , biu f sys , clock 1 , f 1 to f 4096 wf 32 , wf 512 system clock is active. (bit 3 at address 63 16 = 0) note: this applies when the pll circuit operation enable bit (bit 1 at address bc 16 ) = 1. internal peripheral devices termination due to hardware reset supply of cpu , biu starts immediately just after termination. operation after hardware reset
power saving functions 7906 group user s manual rev.2.0 16-7 16.3 stop of oscillation circuit, 16.4 pin v ref disconnection 16.3 stop of oscillation circuit when a stable clock externally generated is input to pin x in , power consumption can be saved by setting the external clock input select bit to 1 to stop the drive circuit for oscillation between pins x in and x out . (see figure 16.1.1.) at this time, the output level at pin x out is fixed to h. also, if the system clock select bit (bit 5 at address bc 16 ) = 0, the watchdog timer is not used when the stop mode is terminated owing to an interrupt request occurrence; therefore, the microcomputer can start instruction execution just after termination of the stop mode. when the system clock select bit = 1, in this case, the watchdog timer is used. 16.4 pin v ref disconnection when the a-d converter is not used, power consumption can be saved by setting the v ref connection select bit (see figure 16.4.1) to 1. it is because the reference voltage input pin (v ref ) is disconnected from the ladder resistors of the a-d converter, and there is no current flow between them. when the v ref connection select bit has been cleared from 1 (v ref disconnected) to 0 (v ref connected), be sure to start the a-d conversion after an interval of 1 s or more has elapsed. fig. 16.4.1 structure of a-d control register 1 0 1 2 3 4 5 6 7 undefined undefined 0 0 0 0 0 0 rw rw rw rw rw rw rw a-d control register 1 (address 1f 16 ) a-d sweep pin select bits (valid in the single sweep mode and repeat sweep mode 0.) (note 1) fix this bit to 0. resolution select bit a-d conversion frequency ( ad ) select bit 1 fix this bit to 0. v ref connection select bit (note 4) the value is 0 at reading. 0 0 : pins an 0 and an 1 (2 pins) 0 1 : pins an 0 to an 3 (4 pins) (note 2) 1 0 : pins an 0 to an 4 (5 pins) (notes 2, 3) 1 1 : do not select. b1 b0 0 : 8-bit resolution mode 1 : 10-bit resolution mode see table 12.2.1. 0 0 : pin v ref is connected. 1 : pin v ref is disconnected. bit name bit function at reset r/w notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1. ) 2: when using pin an 3 , be sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: when using pin an 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 4: when this bit is cleared from 1 to 0, be sure to start the a-d conversion after an interval of 1 s or more has elapsed. 5: writing to each bit of the a-d control register 1 must be performed while the a-d converter halts, regardless of the a-d operation mode. 0
power saving functions 7906 group user s manual rev.2.0 16-8 16.4 pin v ref disconnection memorandum
chapter 17 debug function 17.1 overview 17.2 block description 17.3 address matching detection mode 17.4 out-of-address-area detection mode [precautions for debug function]
debug function 7906 group user? manual rev.2.0 17-2 17.1 overview, 17.2 block description 17.1 overview when the cpu fetches an op code (op-code fetch), the debug function generates an address matching detection interrupt request if a selected condition is satisfied as a result of comparison between the address where the op code to be fetched is stored (in other words, the contents of pg and pc) and the specified address. the debug function provides the following 2 modes: (1) address matching detection mode when the contents of pg and pc match with the specified address, an address matching detection interrupt request occurs. this mode can be used for avoiding or modifying a portion of a program. (2) out-of-address-area detection mode when the contents of pg and pc go out of the specified area, an address matching detection interrupt request occurs. this mode can be used for the program runaway detection by specifying the area where a program exists. note that an address matching detection interrupt is a non-maskable software interrupt. for details of this interrupt, refer to ?hapter 6. interrupts. in addition, the debug function cannot be evaluated by a debugger. therefore, do not use a debugger when using the debug function. 17.2 block description figure 17.2.1 shows the block diagram of the debug function, and the registers relevant to this function are described in the following. fig. 17.2.1 block diagram of debug function address compare register 0 address compare register 1 debug control register 0 matching compare register matching compare register address matching detect circuit debug control register 1 internal data bus (db 0 to db 15 ) cpu bus (address) address matching detection interrupt
debug function 7906 group user s manual rev.2.0 17-3 17.2 block description 17.2.1 debug control register 0 figure 17.2.2 shows the structure of the debug control register 0. (1) detect condition select bits (bits 0 to 2) these bits are used to select an occurrence condition for an address matching detection interrupt request. this condition can be selected from the following: address matching detection 0 an address matching detection interrupt request occurs when the contents of pg and pc match with the address being set in the address compare register 0 (addresses 68 16 to 6a 16 ); (refer to section ?7.3 address matching detection mode. ) address matching detection 1 an address matching detection interrupt request occurs when the contents of pg and pc match with the address being set in the address compare register 1 (addresses 6b 16 to 6d 16 ); (refer to section ?7.3 address matching detection mode. ) address matching detection 2 an address matching detection interrupt request occurs when the contents of pg and pc match with the address being set in the address compare register 0 (addresses 68 16 to 6a 16 ) or address compare register 1 (addresses 6b 16 to 6d 16 ); (refer to section ?7.3 address matching detection mode. ) out-of-address-area detection an address matching detection interrupt request occurs when the contents of pg and pc are less than the address being set in the address compare register 0 (addresses 68 16 to 6a 16 ) or larger than the address compare register 1 (addresses 6b 16 to 6d 16 ); (refer to section ?7.4 out-of- address-area detection mode. ) fig. 17.2.2 structure of debug control register 0 0 1 2 3 4 5 6 7 notes 1: these bits are valid when the detect enable bit (bit 5) = 1. therefore, these bits must be set before or simultaneously with setting of the detect enable bit to 1. 2: at power-on reset, each bit becomes 0 ; at hardware reset or software reset, each bit retains the value immediately before reset. bit name bit debug control register 0 (address 66 16 ) function detect condition select bits (note 1) fix these bits to 00. detect enable bit fix this bit to 0. the value is 1 at reading. rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : do not select. 0 0 1 : address matching detection 0 0 1 0 : address matching detection 1 0 1 1 : address matching detection 2 1 0 0 : do not select. 1 0 1 : out-of-address-area detection 1 1 0 : 1 1 1 : b2 b1 b0 0 : detection disabled. 1 : detection enabled. (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) 1 do not select. 000 at reset r/w
debug function 7906 group user s manual rev.2.0 17-4 17.2.2 debug control register 1 figure 17.2.3 shows the structure of the debug control register 1. fig. 17.2.3 structure of debug control register 1 (1) address compare register access enable bit (bit 2) setting this bit to 1 enables reading from or writing to the contents of address compare registers 0 and 1 (addresses 68 16 to 6d 16 ), while clearing this bit to 0 disables this reading or writing. be sure to set this bit to 1 immediately before reading from or writing to the address compare registers 0 and 1, and then clear it to 0 immediately after this reading or writing. (2) address-matching-detection 2 decision bit (bit 6) when the address matching detection 2 is selected, this bit is used to decide which of the addresses being set in the address compare registers 0 and 1 matches with the contents of pg and pc. this bit is cleared to 0 when the contents of pg and pc matches with the address being set in address compare register 0 and set to 1 when the contents of pg and pc match with the one being set in the address compare register 1. this bit is invalid when the address matching detection 0 and 1 are selected. (note 1) (note 1) 0 0 undefined 0 0 0 0 1 2 3 4 5 6 7 rw ro rw rw ro ro bit name bit debug control register 1 (address 67 16 ) function at reset r/w fix this bit to 0. the value is 0 at reading. address compare register access enable bit (note 2) fix this bit to 1 when using the debug function. nothing is assigned. while a debugger is not used, the value is 0 at reading. while a debugger is used, the value is 1 at reading. address-matching-detection 2 decision bit (valid when the address match- ing detection 2 is selected.) the value is 0 at reading. 0 0 : disabled. 1 : enabled. 0 : matches with the contents of the address com- pare register 0. 1 : matches with the contents of the address com- pare register 1. 1 notes 1: at power-on reset, each bit become 0 ; at hardware reset or software reset, each bit retains the value immediately before reset. 2: be sure to set this bit to 1 immediately before the access to the address compare registers 0 and 1 (addresses 68 16 to 6d 16 ). then, be sure to clear this bit to 0 immediately after this access. b7 b6 b5 b4 b3 b2 b1 b0 17.2 block description (2) detect enable bit (bit 5) if any selected condition is satisfied when this bit = 1, an address matching detection interrupt request occurs.
debug function 7906 group user s manual rev.2.0 17-5 17.2 block description 17.2.3 address compare registers 0 and 1 each of the address compare registers 0 and 1 consists of 24 bits, and the address to be detected is set here. figure 17.2.4 shows the structures of the address compare registers 0 and 1. at op-code fetch, the contents of pg and pc are compared with the addresses being set in the address compare register 0 or 1. therefore, be sure to set the start address of an instruction into the address compare register 0 or 1. if such an address as in the middle of instructions or in the data table is set into the address compare register 0 or 1, no address matching detection interrupt request occurs because this address does not match with the contents of pg and pc. note that, before the instruction at the address being set in the address compare register 0 or 1 is executed, an address matching detection interrupt request occurs and is accepted. fig. 17.2.4 structures of address compare registers 0 and 1 address compare register 0 (addresses 6a 16 to 68 16 ) address compare register 1 (addresses 6d 16 to 6b 16 ) undefined 23 to 0 bit function at reset r/w the address to be detected (in other words, the start address of instructions) is set here. rw b0 b7 b7 b0 b7 (b23) (b8) (b15) (b16) b0 note: when accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 67 16 ) to 1 immediately before the access. then, be sure to clear this bit to 0 immediately after this access.
debug function 7906 group user s manual rev.2.0 17-6 17.3 address matching detection mode 17.3 address matching detection mode when the contents of pg and pc match with the specified address, an address matching detection interrupt request occurs. 17.3.1 setting procedure for address matching detection mode figure 17.3.1 shows an initial setting example for registers relevant to the address matching detection mode. fig. 17.3.1 initial setting example for registers relevant to address matching detection mode selection of detect condition b7 b0 debug control register 0 (address 66 16 ) 00 0 0 0 1 : address matching detection 0 0 1 0 : address matching detection 1 0 1 1 : address matching detection 2 b1 b0 b2 detect enable bit 0 : detection disabled. detect condition select bits detection starts. 0 processing for setting of address compare registers b7 b0 debug control register 1 (address 67 16 ) 11 address compare register access enable bit (note 1) 1 : enabled. b23 b0 address compare register 0 (addresses 6a 16 to 68 16 ) address compare register 1 (addresses 6d 16 to 6b 16 ) the address to be detected is set here. setting of address compare registers b7 b0 debug control register 1 (address 67 16 ) 0 address compare register access enable bit (note 1) 0 : disabled. set the detect enable bit to 1. b7 b0 debug control register 0 (address 66 16 ) detect enable bit 1 : detection enabled. 1 0 disables interrupts. the interrupt disable flag (i) is set to 1. clear the interrupt disable flag (i) to 0 (note 2) . notes 1: be sure to set this bit to 1 immediately before reading from or writing to the address compare registers 0, 1. then, be sure to clear this bit to 0 immediately after this reading or writing. 2: this processing is unnecessary when no maskable interrupt is used.
debug function 7906 group user s manual rev.2.0 17-7 17.3 address matching detection mode 17.3.2 operations in address matching detection mode ? setting the detect enable bit to 1 initiate to compare the contents of pg and pc with one of the con- tents of the following registers. this comparison is performed at each op-code fetch: when the address matching detection 0 is selected, the contents of the address compare register 0 are used for the above comparison. when the address matching detection 1 is selected, the contents of the address compare register 1 are used for the above comparison. when the address matching detection 2 is selected, the contents of the address compare register 0 or 1 are used for the above comparison. ? when the address which matches with the above register s contents is detected, an address matching detection interrupt request occurs, and then, this request will be accepted. ? perform the necessary processing with an address matching detection interrupt routine. ? the contents of pg, pc, and ps at acceptance of the address matching detection interrupt request are saved onto the stack area. therefore, be sure to rewrite the above contents of pg and pc to a certain return address, and return to the address by using the rti instruction. when an address matching detection interrupt request has been accepted, the interrupt disable flag (i) is set to 1 ; the processor interrupt priority level (ipl) does not change. figures 17.3.2 and 17.3.3 show the examples of the rom correct processing using the address matching detection mode.
debug function 7906 group user s manual rev.2.0 17-8 17.3 address matching detection mode fig. 17.3.2 example of rom correct processing using address matching detection mode (1) address matching detection interrupt routin e address matching detection 0 or 1 selected main routine defective or former program top_bu g top_rt n modified or updated progra m the contents of pg and pc saved onto the stack area (address top_bug) are rewritten to address top_rtn (note 2) . rt i top_bug : the start address of defective or former program. this address is to be set in the address compare register 0 or 1, in advance. top_rtn : the address next to the defective or former program. notes 1: when an address matching detection interrupt request has been accepted, the interrupt disable flag (i) is set to 1. if another interrupt requests is required to be accepted under the same conditions as those of the defective or former program, be sure to clear the interrupt disable flag (i) to 0 at the start of an address matching detection interrupt routine. 2: each status of pg, pc, and ps immediately before acceptance of an address matching detection interrupt request is saved onto the stack area. (the contents of pg, pc, and ps are saved onto the stack area in this order.) refer to section 6.7 sequence from acceptance of interrupt request until execution of interrupt routine. 3: make sure that this instruction is executed in the absolute long addressing mode. the above is just an example. in an actual programming, be sure to refer to the format of the assembler description to be used. the interrupt disable flag (i) is cleared to 0 (note 1) stab a, lg : 0h (note 3)
debug function 7906 group user s manual rev.2.0 17-9 17.3 address matching detection mode fig. 17.3.3 example of rom correct processing using address matching detection mode (2) address matching detection interrupt routine address matching detection 2 selected main routine defective or former program ? top_bug1 top_rtn1 modified or updated program ? the contents of pg and pc saved onto the stack area (address top_bug1) are rewritten to address top_rtn1 (note 2) . rt i top_bug1 : the start address of defective or former program ? . this address is to be set in the address compare register 0, in advance. top_rtn1 : the address next to the defective or former program ? . top_bug2 : the start address of defective or former program ? . this address is to be set in the address compare register 1, in advance. top_rtn2 : the address next to the defective or former program ? . notes 1: when an address matching detection interrupt request has been accepted, the interrupt disable flag (i) is set to 1. if another interrupt requests is required to be accepted under the same conditions as those of the defective or former program, be sure to clear the interrupt disable flag (i) to 0 at the start of an address matching detection interrupt routine. 2: each status of pg, pc, and ps immediately before acceptance of an address matching detection interrupt request is saved onto the stack area. (the contents of pg, pc, and ps are saved onto the stack area in this order.) refer to section 6.7 sequence from acceptance of interrupt request until execution of interrupt routine. 3: make sure that this instruction is executed in the absolute long addressing mode. the above is just an example. in an actual programming, be sure to refer to the format of the assembler description to be used . defective or former program ? top_bug2 top_rtn2 address-matching- detection 2 decision bit ? modified or updated program ? the contents of pg and pc saved onto the stack area (address top_bug2) are rewritten to address top_rtn2 (note 2) . 1 0 the interrupt disable flag (i) is cleared to 0 (note 1) stab a, lg : 0h (note 3)
debug function 7906 group user s manual rev.2.0 17-10 17.4 out-of-address-area detection mode 17.4 out-of-address-area detection mode when the contents of pg and pc go out of the range of the specified area, an address matching detection interrupt request occurs. 17.4.1 setting procedure for out-of-address-area detection mode figure 17.4.1 shows an initial setting example for registers relevant to the out-of-address-area detection mode. fig. 17.4.1 initial setting example for registers relevant to out-of-address-area detection mode notes 1: be sure to set this bit to 1 immediately before reading from or writing to the address compare registers 0, 1. then, be sure to clear this bit to 0 immediately after this reading or writing. 2: this processing is unnecessary when no maskable interrupt is used. selection of detect condition b7 b0 debug control register 0 (address 66 16 ) 00 0 detect enable bit 0 : detection disabled. selection of out-of-address-area detection detection starts. 0 processing for setting of address compare registers b7 b0 debug control register 1 (address 67 16 ) 11 address compare register access enable bit (note 1) 1 : enabled. b23 b0 address compare register 0 (addresses 6a 16 to 68 16 ) the start address of the programming area is set here. setting of address compare registers b7 b0 debug control register 1 (address 67 16 ) 0 address compare register access enable bit (note 1) 0 : disabled. set the detect enable bit to 1. b7 b0 debug control register 0 (address 66 16 ) detect enable bit 1 : detection enabled. 1 0 disables interrupts. the interrupt disable flag (i) is set to 1. clear the interrupt disable flag (i) to 0 (note 2) . 01 1 b23 b0 address compare register 1 (addresses 6d 16 to 6b 16 ) the last address of the programming area is set here.
debug function 7906 group user s manual rev.2.0 17-11 17.4 out-of-address-area detection mode 17.4.2 operations in out-of-address-area detection mode ? setting the detect enable bit to 1 initiate to compare the contents of pg and pc with the contents of the address compare registers 0 and 1. ? when an address less than the contents of the address compare registers 0 or larger than the one of the address compare register 1 is detected, an address matching detection interrupt request occurs, and then, this request will be accepted. ? perform the necessary processing with an address matching detection interrupt routine. ? the contents of pg, pc, and ps at acceptance of the address matching detection interrupt request are saved onto the stack area. therefore, be sure to rewrite the above contents of pg and pc to a certain return address, and return there by using the rti instruction. when an address matching detection interrupt request has been accepted, the interrupt disable flag (i) is set to 1 ; the processor interrupt priority level (ipl) does not change. by setting the start address of the programming area into the address compare register 0 and the last address of the programming area into the address compare register 1, a program runaway (in other words, fetching op codes from the area out of the programming area) can be detected. if any program runaway is detected and reset of the microcomputer is required, be sure to write 1 into the software reset bit (bit 6 at address 5e 16 ) within an address matching detection interrupt routine. figure 17.4.2 shows an example of program runaway detection using the out-of-address-area detection mode. fig. 17.4.2 example of program runaway detection using out-of-address-area detection mode top_prg : start address of programming area this address is to be set into the address compare register 0, in advance. end_prg : last address of programming area this address is to be set into the address compare register 1, in advance. note: a program runaway may affect the contents of the data bank register (dt), the direct page registers (dpri) etc. therefore, the contents of these registers must be rewritten in order to write 1 to the software reset bit with an addressing mode using dt, dpri, etc. address matching detection interrupt routine rti software reset bit 1 (note) (bit 6 at address 5e 16 ) the microcomputer is reset. 000000 16 top_prg end_prg ffffff 16 access to the area out of the progra- mming area access to the area out of the programming area programming area
debug function 7906 group user s manual rev.2.0 17-12 [precautions for debug function] [precautions for debug function] 1. the debug function cannot be evaluated by a debugger. therefore, do not use a debugger when using the debug function. 2. when returning from an address matching detection interrupt routine, be sure to rewrite the saved contents of pg and pc to a certain return address, and then return there by using the rti instruction. however, this is unnecessary processing when the software reset is performed within an address matching detection interrupt routine for program runaway detection, etc. 3. be sure to set the start address of an instruction into the address compare register 0 or 1.
chapter 18 applications 18.1 application examples
applications 7906 group user? manual rev.2.0 18-2 18.1 application examples some application examples are described below. each application described here is just an example. therefore, before actual using it, be sure to properly modify it according to the user? system and sufficiently evaluate it. 18.1 application examples 18.1.1 application example of air-conditioner outdoor unit figure 18.1.1 shows an application example of the air-conditioner outdoor unit. fig. 18.1.1 application example of air-conditioner outdoor unit fan motor compressor interface with indoor mcu main-control mcu compressor control mcu m37906 u u v v w w i p m fan-motor control mcu m37906 u u v v w w m o s serial interface serial interface position signal output-forcibly-cutoff signal input output-forcibly-cutoff signal input ac motor dc motor f e t
applications 7906 group user s manual rev.2.0 18-3 18.1 application examples 18.1.2 application example of refrigerator figure 18.1.2 shows an application example of the refrigerator. fig. 18.1.2 application example of refrigerator compressor ipm thermal sensor 1 (inside) thermal sensor 2 (inside) thermal sensor 3 (inside) thermal sensor 4 (inside) sw input door open/close input 4 2 2 2 2 serial interface output-forcibly-cutoff signal input motor control mcu m37906 control mcu u u v v w w
applications 7906 group user s manual rev.2.0 18-4 18.1 application examples fig. 18.1.3 application example of washing machine 18.1.3 application example of washing machine figure 18.1.3 shows an application example of the washing machine. motor contorol mcu m37906 serial interface u u v v w w panel control mcu sw input led output buzzer output position signals motor control voltage cover open/close input sensor water level sensor 1 water level sensor 2 water level sensor 3 output-forcibly-cutoff signal input 3 i p m m
chapter 19 flash memory version 19.1 overview 19.2 flash memory cpu reprogramming mode [precautions for flash memory cpu reprogramming mode] 19.3 flash memory serial i/o mode [precautions for flash memory serial i/o mode] 19.4 flash memory parallel i/o mode [precautions for flash memory parallel i/o mode]
flash memory version 7906 group user? manual rev.2.0 19-2 19.1 overview 19.1 overview the flash memory version is provided with the same function as that of the mask rom version except that the former includes the flash memory. note that, however, part of the sfr area of the flash memory version differs from that of the mask rom version. (refer to section ?9.1.1 memory assignment. ) also, the stop mode terminate operation of the flash memory version differs from that of the mask rom version. (refer to section ?9.1.2 single-chip mode. ) in the flash memory version, its internal flash memory can be handled in the following three reprogramming modes: flash memory cpu reprogramming mode, flash memory serial i/o mode, and flash memory parallel i/o mode. table 19.1.1 lists the performance overview of the flash memory version. (for the items not listed in table 19.1.1, see table 1.1.1.) table 19.1.1 performance overview of flash memory version item performance power source voltage programming/erase voltage flash memory reprogramming modes programming erase method maximum number of reprograms (programming and erasure) 5 v ?0.5 v 5 v ?0.5 v flash memory cpu reprogramming mode, flash memory serial i/o mode, flash memory parallel i/o mode programmed in a unit of word programmed in a unit of byte block erase or total erase 100 for the flash memory version, in addition to the same single-chip mode as that of the mask rom version, any of the operating modes listed in table 19.1.2 can further be selected by the voltage levels applied to pins md1 and md0. table 19.1.3 also lists the overview of flash memory reprogramming modes. note: do not switch the voltages applied to pins md0 and md1 while the microcomputer is active. table 19.1.2 o perating mode selection according to voltages applied to pins md0 and md1 single-chip mode (note 1) boot mode (note 2) flash memory parallel i/o mode (note 3) v ss v cc v ss v cc md1 v ss v ss v cc v cc md0 operating modes notes 1: do not select. 2: refer to section ?9.1.3 boot mode. 3: refer to section ?9.4 flash memory parallel i/o mode. cpu reprogramming mode, flash memory serial i/o mode flash memory parallel i/o mode
flash memory version 7906 group user? manual rev.2.0 19-3 19.1 overview table 19.1.3 overview of flash memory reprogramming modes flash memory reprogramming mode functional overview reprogrammable area operating mode available rom programmer available flash memory cpu reprogramming mode flash memory serial i/o mode flash memory parallel i/o mode user rom area is reprogram- med by using a dedicated serial programmer. user rom area boot mode serial programmer (note) boot rom area and user rom area are reprogrammed by using a dedicated parallel programmer. user rom area, boot rom area flash memory parallel i/o mode parallel programmer (note) user rom area is reprogrammed by the cpu executing software commands. user rom area single-chip mode, boot mode (unnecessary) note: for details of the serial and parallel programmers, please visit mitsubishi tool homepage ( http:/ /www.tool-spt.maec.co.jp/index_e.htm ).
flash memory version 7906 group user? manual rev.2.0 19-4 19.1 overview 19.1.1 memory assignment figure 19.1.1 shows the memory assignment of the m37906f8. fig. 19.1.1 memory assignment of m37906f8 sfr area unused area bank 0 16 internal ram area (3 kbytes) internal flash memory area (user rom area) (60 kbytes) m37906f8 0 16 ff 16 100 16 3ff 16 400 16 fff 16 1000 16 ffff 16
flash memory version 7906 group user s manual rev.2.0 19-5 19.1 overview in addition to the internal flash memory area (in other words, user rom area) shown in figure 19.1.1, the flash memory version has the boot rom area of 8 kbytes. figure 19.1.2 shows the memory assignment of the internal flash memory. the user rom area is divided into several blocks. the user rom area is reprogrammed in the flash memory cpu reprogramming mode, serial i/o mode, and parallel i/o mode. the boot rom area is assigned at addresses, overlapping with the user rom area, however, the boot rom area exists in the defferent memory; the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. (refer to section ?9.4 flash memory parallel i/o mode. ). when being reset with pin md1 tied to vcc level and pin md0 to vss level, the software in the boot rom area is executed after reset. (refer to section ?9.1.3 boot mode. ) when pin md1 = vss level, however, the contents of the boot rom area cannot be read out. fig. 19.1.2 memory assignment of internal flash memory 28 kbytes 16 kbytes 8 kbytes 8 kbytes 8 kbytes (note) user rom area boot rom area (in boot mode) (in flash memory parallel i/o mode) note: addresses ff90 16 to ff9f 16 are reserved for serial and parallel programmers. be sure not to use this area. 1000 16 7fff 16 8000 16 bfff 16 c000 16 dfff 16 e000 16 e000 16 0 16 ffff 16 ffff 16 1fff 16 m37906f8
flash memory version 7906 group user s manual rev.2.0 19-6 19.1 overview 19.1.2 single-chip mode when being reset with both of pins md1 and md0 tied to vss level, the microcomputer enters the single- chip mode. in the single-chip mode, the software in the user rom area is executed after reset. the difference between the flash memory version and the mask rom version is as follows: stop mode terminate operation (1) stop mode terminate operation figure 19.1.3 shows stop mode terminate sequence owing to an interrupt request occurrence in the flash memory version. (refer from section stop mode .) in the flash memory version, when the watchdog timer is not used for termination of the stop mode, an interrupt request is accepted after a maximum of 10 s has elapsed since the interrupt request occurred.
flash memory version 7906 group user s manual rev.2.0 19-7 19.1 overview fig. 19.1.3 stop mode terminate sequence owing to interrupt request occurrence interrupt request to be used for termination occurs. clock input from pin x in starts. watchdog timer starts counting. operating operating operating operating operating stopped stopped stopped internal peripheral device when not using the watchdog timer 10 s (max.) operating operating operating stopped stopped stopped operate operate cpu internal peripheral device interrupt request to be used for termination occurs. oscillation stars. (when an external clock is input from pin x in , clock input starts.) pll frequency multiplier starts its operation. watchdog timer starts counting. value of watchdog timer value of the watchdog timer interrupt request to be used for stop mode termination (interrupt request bit) interrupt request to be used for stop mode termination (interrupt request bit) fff 16 7ff 16 watchdog timer's msb = 0 (however, watchdog timer interrupt request dose not occur.) each supply of cpu, biu starts. interrupt request which was used for termination is accepted. stop mode fx in biu 1 stp instruction is executed. when using the watchdog timer f pll (note) fx i ? 2048 counts note: this applies when the pll circuit operation enable bit (bit 1 at address bc 16 ) = 1. fx i : fx 16 , fx 32 , fx 64, fx 128 there are clocks selected by the watchdog timer clock source bits at stp termination (bits 6, 7 at address 61 16 ) stp instruction is executed. fx in biu 1 stop mode cpu fff 16 7ff 16 each supply of cpu, biu starts. interrupt request which was used for termination is accepted.
flash memory version 7906 group user s manual rev.2.0 19-8 19.1 overview 19.1.3 boot mode when being reset with pin md1 tied to vcc level and pin md0 to vss level, the flash memory version enters the boot mode. in the boot mode, the software in the boot rom area is executed after reset. in the boot mode, either the boot rom area or the user rom area can be selected with the user rom area select bit (bit 5 at address 9e 16 ). the boot rom area is located at addresses e000 16 to ffff 16 in the boot mode. a reprogramming control firmware used in the flash memory serial i/o mode has been stored in the boot rom area on shipment. (refer to section 19.3 flash memory serial i/o mode. ) therefore, when being reset in the boot mode, the flash memory version enters the flash memory serial i/o mode, allowing the user rom area to be reprogrammed with a dedicated serial programmer. also the boot rom area can be reprogrammed in the flash memory parallel i/o mode. if an appropriate reprogramming control software using the cpu reprogramming mode has been stored in the boot rom area, reprogramming suitable for the user s system is enabled. note that if the boot rom area has been reprogrammed in the flash memory parallel i/o mode, the flash memory serial i/o mode cannot be used.
flash memory version 7906 group user? manual rev.2.0 19-9 19.2 flash memory cpu reprogramming mode 19.2 flash memory cpu reprogramming mode in this mode, the user rom area can be reprogrammed by the central processing unit (cpu) executing software commands. therefore, this mode allows the user to reprogram the contents of the user rom area with the microcomputer mounted on the final printed circuit board, without using any rom programmer. be sure to store the reprogramming control software into the user rom area or the boot rom area in advance. in the flash memory cpu reprogramming mode, however, an opcode cannot be fetched for the internal flash memory. accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory area (e.g. the internal ram area), and then execute the software in this area. the flash memory cpu reprogramming mode is available in any of the single-chip and boot modes. the software commands listed in table 19.2.1 can be used in the flash memory cpu reprogramming mode. for details of each command, refer to section ?9.2.4 software commands. note that commands and data must be read from and written into even-numbered addresses within the user rom area, 16 bits at a time. at writing of software command codes, the high-order 8 bits (d 8 to d 15 ) are ignored. (except for the write data at the 2nd bus cycle of the programming command code.) srd : status register data (d 0 to d 7 ) wa : write address (a 7 to a 0 to be incremented by 2 from ?0 16 ?to ?e 16 ? wd : write data (16 bits) ba : the highest address of a block (note that a 0 = 0.) ? : arbitrary even-numbered address in user rom area (a 0 = 0) table 19.2.1 software commands write write write write write write ? ? ? ? ? ? ff 16 70 16 50 16 40 16 20 16 20 16 read write write write srd wd d0 16 20 16 read array read status register clear status register programming block erase erase all blocks ? wa ba ? mode address data (d 0 to d 7 ) mode address 1st bus cycle 2nd bus cycle data software commands
flash memory version 7906 group user? manual rev.2.0 19-10 19.2 flash memory cpu reprogramming mode 19.2.1 flash memory control register figure 19.2.1 shows the structure of the flash memory control register. (1) ry/by status bit (bit 0) this bit is used to indicate the operating status of the sequencer. this bit is ??during the automatic programming or erase operation is active and becomes ??upon completion of them. this bit also changes during the execution of the programming, block erase, or erase all blocks command, but does not change owing to the execution of another command. (2) cpu reprogramming mode select bit (bit 1) setting this bit to ??allows the microcomputer to enter the flash memory cpu reprogramming mode to accept commands. in order to set this bit to ?,?write ??followed with ??successively; while to clear this bit to ?,?write ?. since the microcomputer enters the flash memory cpu reprogramming mode after setting this bit to ?,?opcodes cannot be fetched for the internal flash memory. accordingly, be sure to execute the instruction to be used for writing to this bit in an area other than the internal flash memory area (e.g. the internal ram area). when executing commands of the flash memory cpu reprogramming mode in the boot mode, be sure to set the user rom area select bit (bit 5) to ?. fig. 19.2.1 structure of flash memory control register 0 1 2 3 4 5 7, 6 ry/by status bit cpu reprogramming mode select bit the value is ??at reading. flash memory reset bit (note 3) the value is ??at reading. user rom area select bit (valid in boot mode) (note 5) the value is ??at reading. ro rw (notes 1, 2) rw (note 4) rw (note 2) 1 0 0 0 0 0 0 bit name bit flash memory control register (address 9e 16 ) function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 : busy (automatic programming or erase operation is active.) 1 : ready (automatic programming or erase operation has been completed.) 0 : flash memory cpu reprogramming mode is invalid. 1 : flash memory cpu reprogramming mode is valid. notes 1: in order to set this bit to ?,?write ??followed with ??successively; while in order to clear this bit ?,?write ?. 2: writing to this bit must be performed in an area other than the internal flash memory. 3: this bit is valid when the cpu reprogramming mode select bit (bit 1) = ?? on the other hand, when the cpu reprogramming mode select bit = ?,?be sure to fix this bit to ?.?rewriting of this bit must be performed with the cpu reprogramming mode select bit = ?. 4: after writing of ??to this bit, be sure to confirm the ry/by status bit (bit 0) becomes ?? and then, write ??to this bit. 5: when md1 = vss level, this bit is invalid. (it may be either 0?or ?.? 0 : access to boot rom area 1 : access to user rom area writing ??into this bit discontinues the access to the internal flash memory. this causes the built-in flash memory circuit being reset.
flash memory version 7906 group user? manual rev.2.0 19-11 19.2 flash memory cpu reprogramming mode (3) flash memory reset bit (bit 3) writing ??to this bit discontinues the access to the user rom area and causes the built-in flash memory control circuit to be reset. after this reset, the microcomputer enters the read array mode to set the ry/by status bit (bit 0) to ?? when this flash memory control circuit is reset with the flash memory reset bit during programming (automatic programming) or erase (automatic erase) operation, that programming or erase operation is discontinued to invalidate the data in the working block. after writing of ??to this bit, be sure to confirm the ry/by status bit (bit 0) becomes ?? and then, write ??to this bit. (4) user rom area select bit (bit 5) this bit is used to select either the boot rom area or the user rom area in the boot mode. in order to access the boot rom area (read out), clear this bit to ?.?on the other hand, in order to access the user rom area (reading out, programming, or erase), set it to ?.?instructions for writing into this bit must be executed in an area other than the internal flash memory (e.g. the internal ram area). note that when md1 = vss level, the user rom area is accessed (being read out) regardless of the contents of this bit.
flash memory version 7906 group user? manual rev.2.0 19-12 19.2 flash memory cpu reprogramming mode 19.2.2 status register the programming and erase operations for the internal flash memory are controlled by the sequencer in the internal flash memory. the status register indicates the completion states (normal or abnormal) of the programming and erase operations. for details of abnormal endings (errors), refer to section ?9.2.5 full status check. table 19.2.2 lists the bit definition of the status register. the contents of the status register can be read out by the read status register command. (refer to section ?9.2.4 software commands. ) (1) programming status bit (sr.4) this bit is set to ??if a programming error has occurred during the automatic programming (the programming) operation and cleared to ??by executing the clear status register command. this bit is also cleared to ??at reset. (2) erase status bit (sr.5) this bit is set to ??if an erase error has occurred during the automatic erase (the block erase or erase all unlocked blocks) operation and cleared to ??by executing the clear status register command. this bit is also cleared to ??at reset. symbol (data bus) status definition ? ? error error sr.0 (d 0 ) sr.1 (d 1 ) sr.2 (d 2 ) sr.3 (d 3 ) sr.4 (d 4 ) sr.5 (d 5 ) sr.6 (d 6 ) sr.7 (d 7 ) programming status erase status terminated normally. terminated normally. data bus: indicates the data bus to be read out when the read status register command has been executed. table 19.2.2 bit definition of status register
flash memory version 7906 group user? manual rev.2.0 19-13 19.2 flash memory cpu reprogramming mode 19.2.3 setting and terminate procedure for flash memory cpu reprogramming mode figure 19.2.2 shows the setting and terminate procedures for the flash memory cpu reprogramming mode. in the flash memory cpu reprogramming mode, opcodes cannot be fetched for the internal flash memory. therefore, be sure to transfer the reprogramming control software to an area other than the internal flash memory and then execute the software in that area. moreover, in order to prevent any interrupt occurrence during the flash memory cpu reprogramming mode, before selecting this mode, be sure to set the interrupt disable flag (i) to ??or set the interrupt priority level to ?00 2 ?(interrupts disabled). also, we recommend to connect pin p6out cut with v cc via a resistor. even in the flash memory cpu reprogramming mode, periodically writing to the watchdog timer is required in order to prevent the watchdog timer interrupt occurrence. at the same time, it is necessary to write to the watchdog timer just before executing the programming, block erase, or erase all blocks command in order to prevent the watchdog timer interrupt occurrence during the automatic programming and erase operation. an interrupt, hardware reset, or software reset, generated in the flash memory cpu reprogramming mode, makes program runaway. if a program runaway has occurred, be sure to push the microcomputer into the power-on reset state. when an interrupt or reset is generated during the programming or erase operation, the contents of the corresponding block becomes invalidated. fig. 19.2.2 setting and terminate procedures for flash memory cpu reprogramming mode jump to the control software transferred in the above procedure . (the subsequent procedures will be executed by the reprogramming control software trans- ferred in the above procedure.) user rom area select bit 1 (only in the boot mode) cpu reprogramming mode select bit 0 user rom area select bit 0 (only in the boot mode ) (note 3) jump to an arbitrary address in the internal flash memory area. the reprogramming control software for the flash memory cpu reprogramming mode is transferred to an area other than the internal flash memory. software command is executed. read array command is executed, or flash memory reset bit 1 flash memory reset bit 0 (notes 1, 2) cpu reprogramming mode select bit 0 cpu reprogramming mode select bit 1 notes 1: before termination of the flash memory cpu reprogramming mode, be sure to execute the read array command or flash memory reset 2: after writing of 1 to the flash memory reset bit, be sure to confirm the ry/by status bit (bit 0 at address 9e 16 ) becomes 1 ; and then, write 0 to this bit. 3: when the flash memory cpu reprogramming mode has been terminated with the user rom area select bit (bit 5 at address 9e 16 ) = 1, the access to the user rom area is selected. . reprogramming control software internal rom bus cycle select bit 0 (bit 7 at address 5f 16 ) interrupt disable flag (i) = 1 or interrupt priority level of each interrupt = 000 2 single-chip mode, or boot mode
flash memory version 7906 group user s manual rev.2.0 19-14 19.2 flash memory cpu reprogramming mode 19.2.4 software commands software commands are described below. software commands and data must be read from and written into even-numbered addresses in the user rom area, 16 bits at a time. at writing of a command code, the high-order 8 bits (d 8 to d 15 ) are ignored. (1) read array command writing command code ff 16 at the 1st bus cycle pushes the microcomputer into the read array mode. when an address to be read is input at the next and the following bus cycles, the contents at the specified address are output to the data bus (d 0 to d 15 ), 16 bits at a time. the read array mode is maintained until another software command is written. (2) read status register command writing command code 70 16 at the 1st bus cycle outputs the contents of the status register to the data bus (d 0 to d 7 ) by a read at the 2nd bus cycle. (see table 19.2.2.) (3) clear status register command writing command code 50 16 at the 1st bus cycle clears two bits (sr.4 and sr.5) of the status register to 0. (see table 19.2.2.) (4) programming this command executes programming, one word at a time. write command code 40 16 at the 1st bus cycle and then write data at the 2nd bus cycle, 16 bits at a time. after writing of one word has been completed, the automatic programming (programming and verification of data) operation is initiated. during the automatic programming operation, be sure not to access the flash memory or not to execute the next command. the completion of the automatic programming can be recognized by the ry/by status bit (bit 0 at address 9e 16 ). after the automatic programming operation has been completed, the result of it can be recognized by reading out the status register. (refer to section 19.2.5 full status check. ) figure 19.2.3 shows the programming operation flowchart. note that, for the areas having already been programmed, be sure to program after an erase (block erase) operation. if the programming command is executed for the areas having already been programmed, no programming error will occur, but the contents of the areas become undefined. fig. 19.2.3 programming operation flowchart full status check start command code 40 16 is written. data is written to an arbitrary write address. programming operation is completed. yes see figure 19.2.6. ry/by status bit = 1 ? (bit 0 at address 9e 16 ) no
flash memory version 7906 group user s manual rev.2.0 19-15 19.2 flash memory cpu reprogramming mode (5) block erase command writing of command code 20 16 at the 1st bus cycle and d0 16 to the highest address (here, a 0 = 0) of the block to be erased at the 2nd bus cycle initiate the automatic erase (erase and erase-verify) operation for the specified block. during the automatic erase operation, be sure not to access the flash memory or not to execute the next command. the completion of the automatic erase operation can be recognized by the ry/by status bit (bit 0 at address 9e 16 ). after the automatic erase operation is completed, the result of it can be recognized by reading out the status register. (refer to section 19.2.5 full status check. ) figure 19.2.4 shows the block erase operation flowchart. (6) erase-all-blocks command writing of command code 20 16 at the 1st bus cycle and 20 16 at the 2nd bus cycle initiate the automatic erase (erase and erase-verify) operation for all the blocks. during the automatic erase operation, be sure not to access the flash memory or not to execute the next command. the completion of the automatic erase operation can be recognized by the ry/by status bit (bit 0 at address 9e 16 ). after the automatic erase operation is completed, the result of it can be recognized by reading out the status register. (refer to section 19.2.5 full status check. ) figure 19.2.5 shows the erase-all-blocks operation flowchart. fig. 19.2.4 block erase operation flowchart fig. 19.2.5 erase-all-blocks operation flowchart full status chec k start command code 20 16 is written. d0 16 is written to the highest address of the block. block erase operation is completed. yes see figure 19.2.6. ry/by status bit = 1 ? (bit 0 at address 9e 16 ) no ye s ry/by status bit = 1 ? (bit 0 at address 9e 16 ) no full status chec k start command code 20 16 is written. 20 16 is written. erase-all-blocks operation is completed. see figure 19.2.6.
flash memory version 7906 group user s manual rev.2.0 19-16 19.2 flash memory cpu reprogramming mode 19.2.5. full status check if an error has occurred, bits sr.4 and sr.5 of the status register are set to 1 upon completion of the programming or erase operation. therefore, the result of the programming or erase operation can be recognized by checking these status (in other words, full status check). table 19.2.3 lists the errors and the states of bits sr.4 and sr.5, and figure 19.2.6 shows the full status check flowchart and the action to be taken if any error has occurred. table 19.2.3 errors and states of bits sr.3 to sr.5 1 1 0 1 0 1 command sequen- ce error erase error programming error commands are not correctly written. data other than d0 16 and ff 16 is written at the 2nd bus cycle of the block erase command (note) . data other than 20 16 and ff 16 is written at the 2nd bus cycle of the erase-all-blocks command (note) . although the block erase or erase-all-blocks command is executed, these blocks are not correctly erased. although the programming command is executed, programming is not correctly performed. error occurrence conditions status register sr.5 sr.4 error notes: when ff 16 is written at the 2nd bus cycle of any of these commands, the microcomputer enters the read array mode. simultaneously with this, the command code written at the 1st bus cycle is cancelled. fig. 19.2.6 full status check flowchart and actions to be taken if any error has ocurred read status register sr.5 = 0? completed. no no yes erase error yes command sequence error sr.4 = 1 and sr.5 = 1 ? sr.4 = 0? no yes programming error ? execute the clear status command to clear sr.4 and sr.5 to 0. ? execute the correct command again. note: if the same error occurs, however, the block cannot be used. note: under the condition that any of sr.4 and sr.5 = 1, none of the programming, block erase, erase-all-blocks commands can be accepted. to execute any of these commands, in advance, execute the clear status register command. ? execute the clear status command to clear sr.5 to 0. ? execute the block erase or erase-all-unlocked-blocks command again. note: if the same error occurs, however, the block cannot be used. ? execute the clear status command to clear sr.4 to 0. ? execute the programming command again. note: if the same error occurs, however, the block cannot be used.
flash memory version 7906 group user s manual rev.2.0 19-17 19.2 flash memory cpu reprogramming mode 19.2.6 electrical characteristics (1) m37906f8cfp v cc power source current (at read) v cc power source current (at write) v cc power source current (at programming) v cc power source current (at erasing) i cc1 i cc2 i cc3 i cc4 ma ma ma ma limits parameter max. min. unit symbol 30 30 40 40 typ. 10 256 bytes programming time block erase time erase all blocks time ms s s limits parameter max. min. unit 40 8 8 ? n typ. 4 0.6 0.6 ? n ac electrical characteristics (v cc = 5 v 0.5 v, ta = 0 to 60 c, f(f sys ) = 20 mhz) dc electrical characteristics (v cc = 5 v 0.5 v, ta = 0 to 60 c, f(f sys ) = 20 mhz) n = number of blocks to be erased for the limits of parameters other than the above, refer to section appendix 9. m37906m4c-xxxfp electrical characteristics.
flash memory version 7906 group user s manual rev.2.0 19-18 [precautions for flash memory cpu reprogramming mode] [precautions for flash memory cpu reprogramming mode] 1. in the flash memory cpu reprogramming mode, an opcode cannot be fetched for the internal flash memory. accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory area, and then execute the software in this area. (see figure 19.2.2.) also, take consideration for instruction description (such as specified addresses, addressing modes) in the repro- gramming control software since this software is to be executed in an area other than the internal flash memory area. 2. in order to prevent any interrupt occurrence during the flash memory cpu reprogramming mode, before selecting this mode, be sure to set the interrupt disable flag (i) to 1 or set the interrupt priority level to 000 2 (interrupts disabled). also, we recommend to connect pin p6out cut with v cc via a resistor. even in the flash memory cpu reprogramming mode, periodically writing to the watchdog timer is required. also, an interrupt, hardware reset, or software reset, generated in the cpu reprogramming mode, makes program runaway. if a program runaway has occurred, be sure to push the microcomputer into the power-on reset state. 3. commands and data must be read from and written into even-numbered addresses in the user rom area, 16 bits at a time. 4. be sure not to execute the stp instruction in the cpu reprogramming mode. 5. in order to reset the internal flash memory control circuit by using the flash memory reset bit (bit 3 at address 9e 16 ), be sure to confirm the ry/by status bit (bit 0 at address 9e 16 ) becomes 1 after writing of 1 to this bit; and then, write 0 to the flash memory reset bit. 6. addresses ff90 16 to ff9f 16 (the user rom area) are reserved for serial and parallel programmers. be sure not to use this area.
flash memory version 7906 group user? manual rev.2.0 19-19 19.3 flash memory serial i/o mode 19.3 flash memory serial i/o mode in the flash memory serial i/o mode, by using a dedicated serial programmer, the contents of the user rom area can be reprogrammed with the microcomputer mounted on the final printed circuit board. about the serial programmer concerned, consult its manufacturer, and for more information on using it, refer to the user? manual of the serial programmer. note that if the boot rom area has been reprogrammed in the flash memory parallel i/o mode, the flash memory serial i/o mode cannot be used. (refer to section ?9.4 flash memory parallel i/o mode. ) addresses ff90 16 to ff9f 16 (the user rom area) are reserved for serial or parallel programmers. therefore, be sure not to use to this area. 19.3.1. pin description table 19.3.1 lists the pin description in the flash memory serial i/o mode, and each of figures 19.3.1 and 19.3.2 shows the pin configuration in this mode.
flash memory version 7906 group user? manual rev.2.0 19-20 19.3 flash memory serial i/o mode table 19.3.1 pin description in flash memory serial i/o mode supply v cc level voltage to pin vcc. supply v ss level voltage to pin vss. connect this pin to v ss . connect this pin to v ss via a resistor (about 10 k ? to 100 k ? ). the reset input pin (note 1) . connect a ceramic resonator or quartz-crystal oscillator between x in and x out pins. when using an external clock, the clcok source must be input to x in pin and x out pin must be left open. the v cont pin. (not used in this mode.) connect this pin to v cc . connect this pin to v ss . the v ref pin. (not used in this mode.) input port pins. (not used in this mode.) the input pin for a serial clock. the i/o pin for serial data. this pin must be connected with v cc via a resistor (about 1 k ? ). the busy signal output pin. input port pins. (not used in this mode.) the p6out cut pin. (not used in this mode.) recommended to be connected with v cc via a resistor. v cc v ss md0 md1 reset x in x out v cont av cc av ss v ref p1 0 to p1 7 p2 0 to p2 3, p2 7 p2 4 p2 5 p2 6 p5 0 to p5 7 p6 0 to p6 5 p7 0 to p7 4 p6out cut input input input input output input input input input i/o output input input input input pin name input/output functions power supply input md0 md1 reset input clock input clock output filter circuit connection analog supply input reference voltage input input port p1 input port p2 sclk input sda i/o busy output input port p5 input port p6 input port p7 p6out cut input notes 1: when there is a possibility that the user reset signal becomes ??level in the flash memory serial i/o mode, be sure to cut off the current flow between the user reset signal and pin reset by using a jumper switch, etc. (refer to section ?9.3.2 examples of handling control pins in flash memory serial i/o mode. ) 2: for pins not used in the flash memory serial i/o mode, properly connect to somewhere in the user system. for pins not used in the user system, handle them with reference to section ?.3 examples of handling unused pins. for pins used in the flash memory serial i/o mode, handle them with reference to section ?9.3.2 examples of handling control pins in flash memory serial i/o mode.
flash memory version 7906 group user? manual rev.2.0 19-21 19.3 flash memory serial i/o mode fig. 19.3.1 pin connection in flash memory serial i/o mode (outline: 42p2r-e) avss 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 v ref p7 4 /an 4 /da 1 /int 3 /rtp trg0 p7 3 /an 3 /da 0 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 md0 v cont vcc avcc p1 2 /r x d 0 p1 3 /t x d 0 p1 6 /r x d 1 p1 7 /t x d 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 4 (/tb0 in ) p2 5 (/tb1 in ) p2 6 (/tb2 in ) md1 x out x in vss p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p6out cut /int 4 reset p2 7 (/int 3 /rtp trg0 ) p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 1 /cts 0 /clk 0 p1 0 /cts 0 /rts 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw notes 1: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switched by software. 2: connected to the oscillation circuit. 3: recommended to be connected with v cc via a resistor. : connected to a serial programmer. (note 3) (note 1) md1 busy sda sclk (note 2) (note 1) (note 1) v cc v ss reset outline 42p2r-e
flash memory version 7906 group user s manual rev.2.0 19-22 19.3 flash memory serial i/o mode fig. 19.3.2 pin connection in flash memory serial i/o mode (outline: 42p4b) avss 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 v ref p7 4 /an 4 /da 1 /int 3 /rtp trg0 p7 3 /an 3 /da 0 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 md0 v cont vcc avcc p1 2 /r x d 0 p1 3 /t x d 0 p1 6 /r x d 1 p1 7 /t x d 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 4 (/tb0 in ) p2 5 (/tb1 in ) p2 6 (/tb2 in ) md1 x out x in vss p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 reset p2 7 (/int 3 /rtp trg0 ) p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 1 /cts 0 /clk 0 p1 0 /cts 0 /rts 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw (note 1) md1 busy sda sclk (note 2) (note 1) (note 1) v cc v ss reset (note 3) p6out cut /int 4 notes 1: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switched by software. 2: connected to the oscillation circuit. 3: recommended to be connected with v cc via a resistor. : connected to a serial programmer. outline 42p4b
flash memory version 7906 group user s manual rev.2.0 19-23 19.3 flash memory serial i/o mode 19.3.2. example of handling control pins in flash memory serial i/o mode each of pins p2 4 to p2 6 , md0, and md1 serves as an input/output pin for a control signal in the flash memory serial i/o mode. examples of handling these pins and pin reset on the board are described below. (1) with control signals not affecting user system circuit when control signals in the flash memory serial i/o mode are not used in the user system circuit, or when these signals do not affect that circuit, the connections shown in figure 19.3.3 are available. when pin p6out cut , however, is used in the user system circuit, see figures 19.3.4 and 19.3.5. fig. 19.3.3 example of handing control pins when control signals do not affect user system circuit p6out cut m37906f user system board reset md1 sda(p2 5 ) busy(p2 6 ) sclk(p2 4 ) x in x ou t user reset signal (note) not used, or connected to the user system circuit note: when there is a possibility that the user reset signal becomes l level in the flash memory serial i/o mode, be sure to cut the current flow between the user reset pin and pin reset by using a jumper switch, etc. v ss v cc md 0 connected to serial progra- mmer. ? : the flash memory version of the 7906 group ?
flash memory version 7906 group user s manual rev.2.0 19-24 19.3 flash memory serial i/o mode (2) with control signals affecting user system circuit in the flash memory serial i/o mode, be sure to cut the current flow toward the user system circuit if control signals for this mode are also used in the user system circuit. figure 19.3.4 shows an example of handling pins with jumper switches used, and figure 19.3.5 shows an example of handling pins with analog switches used. fig. 19.3.4 example of handling pins with jumper switches used fig. 19.3.5 example of handling pins with analog switches used m37906f rese t user reset signal (note 2) user system board connected to the user system circuit. md1 sda(p2 5 ) busy(p2 6 ) sclk(p2 4 ) x in x ou t p6out cut (note 1) v ss v cc md 0 connected to serial progra- mmer. note 1: recommended to be connected with v cc via a resistor. 2: when there is a possibility that the user reset signal becomes l level in the flash memory serial i/o mode, be sure to cut the current flow between the user reset pin and pin reset by using a jumper switch, etc. ? : the flash memory version of the 7906 group ? rese t md1 sda(p2 5 ) busy(p2 6 ) sclk(p2 4 ) x in x ou t p6out cut v ss v cc md 0 74 h c4066 user system board connected to the user system circuit. m37906f ? (note 1) connected to serial progra- mmer. user reset signal (note 2) ? : the flash memory version of the 7906 group note 1: recommended to be connected with v cc via a resistor. 2: when there is a possibility that the user reset signal becomes l level in the flash memory serial i/o mode, be sure to cut the current flow between the user reset pin and pin reset by using a jumper switch, etc.
flash memory version 7906 group user s manual rev.2.0 19-25 [precautions for flash memory serial i/o mode] [precautions for flash memory serial i/o mode] 1. if the boot rom area has been reprogrammed in the flash memory parallel i/o mode, the flash memory serial i/o mode cannot be used. 2. in the flash memory serial i/o mode, we recommend to connect pin p6out cut with v cc via a resistor. (refer to section 19.3.2 examples of handling control pins in flash memory serial i/o mode. ) 3. when there is a possibility that the user reset signal becomes l level in the flash memory serial i/o mode, be sure to cut the current flow between the user reset pin and pin reset by using a jumper switch, etc. (refer to section 19.3.2 examples of handling control pins in flash memory serial i/o mode. ) 4. addresses ff90 16 to ff9f 16 (the user rom area) are reserved for serial and parallel programmers. therefore, be sure not to use this area.
flash memory version 7906 group user s manual rev.2.0 19-26 19.4 flash memory parallel i/o mode 19.4 flash memory parallel i/o mode in the flash memory parallel i/o mode, the contents of the user rom area and boot rom area can be reprogrammed by using a dedicated parallel programmer. (see figure 19.1.2.) about the parallel programmer concerned, consult its manufacturer, and for more information on using it, refer to the user s manual of the parallel programmer. in the flash memory parallel i/o mode, the boot rom area is assigned to addresses 0 16 to 1ffff 16 (word addresses). note that if the boot rom area has been reprogrammed in the flash memory parallel i/o mode, the flash memory serial i/o mode cannot be used. (refer to section 19.3 flash memory serial i/o mode. ) also, addresses ff90 16 to ff9f 16 (the user rom area) are reserved for serial and parallel programmers. therefore, besure not to use this area.
flash memory version 7906 group user s manual rev.2.0 19-27 [precautions for flash memory parallel i/o mode] [precautions for flash memory parallel i/o mode] 1. if the boot rom area has been reprogrammed in the flash memory parallel i/o mode, the flash memory serial i/o mode cannot be used. (refer to section 19.3 flash memory serial i/o mode. ) 2. addresses ff90 16 to ff9f 16 (the user rom area) are reserved for serial and parallel programmers. be sure not to use this area.
flash memory version 7906 group user s manual rev.2.0 19-28 [precautions for flash memory parallel i/o mode] memorandum
appendix appendix 1. memory assignment in sfr area appendix 2. control registers appendix 3. package outline appendix 4. examples of handling unused pins appendix 5. hexadecimal instruction code table appendix 6. machine instructions appendix 7. countermeasure against noise appendix 8. 7906 group q & a appendix 9. m37906m4c-xxxfp electrical characteristics appendix 10. m37906m4c-xxxfp standard characteristics appendix 11. memory assignment of 7906 group
7906 group user? manual rev.2.0 appendix 20-2 appendix 1. memory assigment in sfr area appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1c 16 1b 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p5 register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register a-d control register 0 a-d control register 1 register name port p1 register port p1 direction register port p2 register port p2 direction register access characteristics state immediately after reset b7 b0 b7 b0 notes 1: do not read from and write to this register. 2: do not write to this register. 0 ? (note 2) ? (note 2) ? (note 2) ? ? 0 ? ? 0 0 0 0 ? rw rw rw rw rw ? ? ? ? ? rw rw 00 16 ? 00 16 rw rw rw ? ? 0 0 ? 0 00 0 0 0 0 ? ? 00 0 00 0 0 00 0 0 (note 1) (note 2) rw (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) ? ? ? ? ? ? ? ? ? ? ? ? ? ? rw ? ? ? (note 1) sfr area (addresses 0 16 to ff 16 )
7906 group user s manual rev.2.0 20-3 appendix appendix 1. memory assigment in sfr area uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart1 receive buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 b7 b0 register name address access characteristics state immediately after reset b7 b0 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 ? ? ? ? (note 4) ? ? ? ? 00 0 0 0 0 rw rw ? 0000 0 0 ? 00 0 0 0 0 ? 00 0 0 0 0 rw wo wo ro ro wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro ro ro rw rw ? ? ? ? 01 0 0 0 ? ? ? 00 16 ? ? ? ? 00000 0 0 ? ? 00 16 0 0 0 0 0 0 1 0 0 0 00 0 0 0 ? 1 0 00 00 00 00 1 0 0 0 0 0 000 ? 000 0 0 0 (note 3) (note 4) (note 4) (note 4) (note 4) (note 4) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) notes 3: the access characteristics at addresses 20 16 to 29 16 vary according to the contents of the comparator function select register 0 (address dc 16 ). (refer to ?hapter 12. a-d converter. ) 4: do not write to this register. : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0
7906 group user s manual rev.2.0 appendix 20-4 appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0 timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start register 0 timer a0 register up-down register 0 timer a1 register count start register 0 timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register b7 b0 b7 b0 timer a0 mode register timer a4 mode register processor mode register 1 timer a clock division select register register name address access characteristics state immediately after reset notes 5: the access characteristics at addresses 46 16 to 4b 16 , 4e 16 , and 4f 16 vary according to the timer a s operating mode. (refer to chapter 7. timer a. ) 6: the access characteristics at addresses 50 16 to 55 16 vary according to the timer b s operating mode. (refer to chapter 8. timer b. ) 7: the access characteristics for bit 5 at addresses 5b 16 to 5d 16 vary according to the timer b s operating mode. (refer to chapter 8. timer b. ) count start register 1 one-shot start register 1 0 1 0 0 0 0 0 0 00 ? 0 00 0 0 ? 0 0 0 wo rw rw rw rw rw rw rw rw wo ? ? ? ? ? ? ? ? ? ? ? ? ? 00 16 00 16 00 16 00 16 ? ? 0 rw rw rw rw rw rw (note 7) 0 0 00 0 0 0 ? ? 00 ? 0 000 0 0 0 rw 0 0 0 0 rw rw (note 6) (note 5) 0 0 0 0 0 00 0 00 16 00 16 rw rw 0 rw rw 0 0 00 0 ? rw 0 0 0 0 0 0 ? wo rw wo 0 1 0 0 0 0 (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 6) (note 6) (note 6) (note 6) (note 6) 0000 0 (note 7) (note 7)
7906 group user s manual rev.2.0 20-5 appendix appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0 uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 a-d conversion interrupt control register uart0 transmit interrupt control register uart1 transmit interrupt control register watchdog timer frequency select register watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register b7 b0 b7 uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register debug control register 0 int 4 interrupt control register b0 int 3 interrupt control register debug control register 1 particular function select register 0 particular function select register 1 address comparison register 0 address comparison register 1 particular function select register 2 register name address access characteristics state immediately after reset notes 8 : by writing dummy data to address 60 16 , a value of fff 16 is set to the watchdog timer. the dummy data is not retained anywhere. 9 : a value of fff 16 is set to the watchdog timer. (refer to chapter 14. watchdog timer. ) 10 : after writing 55 16 to address 62 16 , each bit must be set. 11 : it is possible to read the bit state at reading. by writing 0 to this bit, this bit becomes 0. but when writing 1 to this bit, this bit will not change. 12 : this bit becomes 0 at power-on reset. this bit retains the state immediately before reset in the case of hardware reset and software reset. 13 : do not write to this register. 14 : when these registers are accessed, set the address comparison register access enable bit (bit 2 at address 67 16 ) to 1. (refer to chapter 17. debug function. ) (note 13) ? 0 0 0 (note 12) 0 0 0 0 0 0 00 0 ? ? ? ? 0 rw 1 0 0 rw (note 8) rw rw rw rw rw rw rw rw rw rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (note 9) 0 0000 0000 ? 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 rw rw rw rw rw rw ro ? ? 0 (note 12) 0 0 000 0 ? 0 (note 12) (note 11) ro ro rw rw rw rw (note 14) rw (note 14) rw (note 14) rw (note 14) rw (note 14) rw (note 14) rw (note 10) 0 (note 13) rw rw rw rw rw 0 0 0 0 ? 0 0 (note 13) ? (note 13) ? ?
7906 group user s manual rev.2.0 appendix 20-6 appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0 80 16 81 16 82 16 83 16 84 16 85 16 86 16 87 16 88 16 89 16 90 16 91 16 92 16 93 16 94 16 95 16 96 16 97 16 98 16 99 16 9a 16 9b 16 9c 16 9d 16 9e 16 9f 16 8b 16 8c 16 8d 16 8e 16 8f 16 8a 16 b7 b0 b7 b0 flash memory control register (note 16) d-a register 1 d-a register 0 d-a control register external interrupt input read-out register register name address access characteristics state immediately after reset notes 15 : do not write to this register. 16 : this register is assigned only to the flash memory version. (refer to chapter 19. flash memory version. ) nothing is assigned here in the mask rom version. ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? ? ? rw 0 0 00 0 0 1 rw ro rw 0 0 rw rw rw rw 00 16 00 16 ? ? ? ? ? ? ? (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) (note 15) ro
7906 group user s manual rev.2.0 20-7 appendix appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0 a0 16 a1 16 a2 16 a3 16 a4 16 a5 16 a6 16 a7 16 a8 16 a9 16 b0 16 b1 16 b2 16 b3 16 b4 16 b5 16 b6 16 b7 16 b8 16 b9 16 ba 16 bb 16 bc 16 bd 16 be 16 bf 16 ab 16 ac 16 ad 16 ae 16 af 16 aa 16 b7 b0 b7 b0 three-phase output data register 1 serial i/o pin control register clock control register 0 notes 17 : do not write to this register. 18 : after reset, these bits are allowed to be changed only once. register name address access characteristics state immediately after reset port p2 pin function control register position-data-retain function control register three-phase output data register 0 dead-time timer waveform output mode register 0 00 0 1 0 1 0 ? ? 00 000 0 0 ? rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rw rw rw rw ? ? ? ? ? ? 1 0 00 1 ? (note 17) rw rw rw rw 0 00 0 ro rw ro ro 00 16 00 16 00 16 ??? rw wo rw rw (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) (note 17) rw rw rw (note 18) rw rw (note 17) (note 17) rw 0
7906 group user s manual rev.2.0 appendix 20-8 appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0 timer a2 1 register c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 timer a7 register timer a8 register timer a9 register timer a0 1 register timer a1 1 register comparator result register 0 timer a5 register up-down register 1 timer a6 register timer a6 mode register timer a7 mode register timer a8 mode register comparator function select register 0 b7 b0 b7 b0 timer a5 mode register timer a9 mode register register name address access characteristics state immediately after reset notes 19: the access characteristics at addresses ce 16 and cf 16 vary according to the timer a s operating mode. (refer to chapter 7. timer a. ) 20: do not write to this register. rw rw 0 0 ? wo ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 (note 20) ? 0 00 000 0 0 ? ? ? ? ? ? ? ? ? (note 19) (note 19) rw 00 16 rw 00 16 rw 00 16 rw 00 16 rw 00 16 wo wo wo wo wo wo rw 0 0 0 0 00 00 0 0 0 rw rw rw rw rw rw rw rw (note 20) (note 20)
7906 group user s manual rev.2.0 20-9 appendix appendix 1. memory assigment in sfr area : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo access characteristics 0 1 ? : 0 immediately after reset. : 1 immediately after reset. : undefined immediately after reset. : always 0 at reading. : always 1 at reading. : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 0 ? 1 state immediately after reset 0 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 timer a5 interrupt control register timer a7 interrupt control register timer a8 interrupt control register timer a9 interrupt control register b7 b0 b7 timer a6 interrupt control register int 7 interrupt control register b0 int 6 interrupt control register register name address access characteristics state immediately after reset notes 21 : do not write to this register. int 5 interrupt control register ? ? ? ? ? (note 21) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rw ? 0000 000 rw 0 ? 0 ? 000 rw 0 ? 000 rw 0 ? 000 rw 0 ? 000 rw 0 rw 0000 0 ? rw 0000 0 ? 0 0 0 (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) (note 21) ?
7906 group user? manual rev.2.0 appendix 20-10 appendix 2. control registers appendix 2. control registers the control registers allocated in the sfr area are shown on the following pages. below is the structure diagram for all registers. xxx register (address xx 16 ) 0 1 2 3 4 5 6 7 ???select bit ???select bit ???flag fix this bit to ?. this bit is invalid in ?mode. nothing is assigned. the value is ??at reading. b7 b6 b5 b4 b3 b2 b1 b0 0 : 1 : 0 : 1 : the value is ??at reading. 0 x 0 0 : 0 1 : 1 0 : 1 1 : b2 b1 ? 1 ? 2 ? 3 ? 5 undefined 0 0 0 0 0 undefined 0 ? 6 wo rw rw ro rw rw ? 1 blank : set to 0 or 1 according to the usage. 0 : set to 0 at writing. 1 : set to 1 at writing. ? : invalid depending on the mode or state. it may be 0 or 1. : nothing is assigned. ? 2 0: 0 immediately after reset. 1: 1 immediately after reset. undefined : undefined immediately after reset. ? 3 rw : it is possible to read the bit state at reading. the written value becomes valid. ro : it is possible to read the bit state at reading. the written value becomes invalid. accordingly, the written value may be 0 or 1. wo : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [ 0 at reading ] is indicated in the function or note column, the bit is always 0 at reading. (see ? 5 above.) : it is impossible to read the bit state. the value is undefined at reading. however, when [ 0 at reading ] is indicated in the function or note column, the bit is always 0 at reading. (see ? 6 above.) the written value becomes invalid. accordingly, the written value may be 0 or 1. ? 4 reference page for each bit. bit name bit function at reset r/w ? 4 reference 3-10 3-11 2-6
7906 group user s manual rev.2.0 20-11 appendix appendix 2. control registers rw rw rw rw rw rw rw rw bit name bit 0 1 2 3 4 5 6 7 port pi register (i = 1, 2, 5 to 7) (addresses 3 16 , 6 16 , b 16 , e 16 , f 16 ) funtion at reset r/w port pin pi 0 port pin pi 1 port pin pi 2 port pin pi 3 port pin pi 4 port pin pi 5 port pin pi 6 port pin pi 7 undefined undefined undefined undefined undefined undefined undefined undefined b7 b6 b5 b4 b3 b2 b1 b0 notes 1: nothing is assigned for bits 0 to 4 of the port p5 register. these bits are undefined at reading. 2: nothing is assigned for bits 6 and 7 of the port p6 register. these bits are undefined at reading. 3: nothing is assigned for bits 5 to 7 of the port p7 register. these bits are undefined at reading. data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : l level 1 : h level reference 5-4 0 1 2 3 4 5 6 7 port pi direction register (i = 1, 2, 5 to 7) (addresses 5 16 , 8 16 , d 16 , 10 16 , 11 16 ) port pi 0 direction bit port pi 1 direction bit port pi 2 direction bit port pi 3 direction bit port pi 4 direction bit port pi 5 direction bit port pi 6 direction bit port pi 7 direction bit 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 notes 1: nothing is assigned for bits 0 to 4 of the port p5 direction register. these bits are undefined at reading. 2: nothing is assigned for bits 6 and 7 of the port p6 direction register. these bits are undefined at reading. 3: nothing is assigned for bits 5 to 7 of the port p7 direction register. these bits are undefined at reading. 4: any of bits 0 to 5 of the port p6 direction register becomes 0 by input of a falling edge to pin p6out cut /int 4 . (refer to section ?.2.3 pin p6out cut /int 4 . ) 0 : input mode (the port functions as an input port.) 1 : output mode (the port functions as an output port.) bit name bit function at reset r/w reference 5-3 port p1 11-18 port p2 6-20 7-10 8-6 9-9 port p5 6-20 8-6 10-13 port p6 5-6 7-10 port p7 6-20 9-9 12-11
7906 group user s manual rev.2.0 appendix 20-12 appendix 2. control registers undefined undefined undefined 0 0 0 0 0 rw rw rw rw rw rw rw (note 4) rw notes 1: these bits are invalid in the single sweep mode and repeat sweep mode 0. (each may be either 0 or 1. ) 2: when using pin an 3 , be sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: when using pin an 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 4: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 5: writing to each bit (except write of 0 to bit 6) of the a-d control register 0 must be performed while the a-d converter halts, regardless of the a-d operation mode. 0 1 2 3 4 5 6 7 a-d control register 0 (address 1e 16 ) analog input pin select bits (valid in the one-shot and repeat modes.) (note 1) a-d operation mode select bits fix this bit to 0. a-d conversion start bit a-d conversion frequency ( ad ) select bit 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : an 0 is selected. 0 0 1 : an 1 is selected. 0 1 0 : an 2 is selected. 0 1 1 : an 3 is selected. (note 2) 1 0 0 : an 4 is selected. (note 3) 1 0 1 : do not select. 1 1 0 : do not select. 1 1 1 : do not select. b2 b1 b0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 b4 b3 bit name bit function at reset r/w reference 12-7 0 : a-d conversion halts. 1 : a-d conversion starts. see table 12.2.1. 0
7906 group user s manual rev.2.0 20-13 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 reference 12-7 12-8 16-7 undefined undefined 0 0 0 0 0 0 rw rw rw rw rw rw rw a-d control register 1 (address 1f 16 ) a-d sweep pin select bits (valid in the single sweep mode and repeat sweep mode 0.) (note 1) fix this bit to 0. resolution select bit a-d conversion frequency ( ad ) select bit 1 fix this bit to 0. v ref connection select bit (note 4) the value is 0 at reading. b7 b6 b5 b4 b3 b2 b1 b0 0 0 : pins an 0 and an 1 (2 pins) 0 1 : pins an 0 to an 3 (4 pins) (note 2) 1 0 : pins an 0 to an 4 (5 pins) (notes 2, 3) 1 1 : do not select. b1 b0 0 : 8-bit resolution mode 1 : 10-bit resolution mode see table 12.2.1. 0 0 : pin v ref is connected. 1 : pin v ref is disconnected. bit name bit function at reset r/w notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1. ) 2: when using pin an 3 , be sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: when using pin an 4 , be sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 4: when this bit is cleared from 1 to 0, be sure to start the a-d conversion after an interval of 1 s or more has elapsed. 5: writing to each bit of the a-d control register 1 must be performed while the a-d converter halts, regardless of the a-d operation mode. 0
7906 group user s manual rev.2.0 appendix 20-14 appendix 2. control registers undefined 0 ro bit 7 to 0 15 to 8 function at reset r/w reads an a-d conversion result. the value is 0 at reading. b0 b7 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) b0 b7 (b15) (b8) when 8-bit resolution mode is selected a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) when 10-bit resolution mode is selected undefined 0 ro 9 to 0 15 to 10 reads an a-d conversion result. the value is 0 at reading. b0 b7 b0 b7 (b15) (b8) bit function at reset r/w reference 12-8 reference 12-8 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) when comparator function is selected undefined 0 ro 7 to 0 15 to 8 any value in the range from 00 16 to ff 16 can be set. the set value is compared with the input voltage. the value is undefined at reading. the value is 0 at reading. b0 b7 b0 b7 (b15) (b8) bit function at reset r/w reference 12-8 note: when the comparator function is selected, writing to and reading from the a-d register i must be performed while the a-d converter halts.
7906 group user s manual rev.2.0 20-15 appendix appendix 2. control registers 8 to 0 15 to 9 reference 11-5 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) serial i/o mode select bits internal/external clock select bit stop bit length select bit (valid in uart mode) (note) odd/even parity select bit (valid in uart mode when parity enable bit = 1. ) (note) parity enable bit (valid in uart mode) (note) sleep select bit (valid in uart mode) (note) rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 note: bits 4 to 6 are invalid in the clock synchronous serial i/o mode. (each may be either 0 or 1. ) additionally, fix bit 7 to 0. 0 0 0 : serial i/o is invalid. (p1 functions as a programmable i/o port.) 0 0 1 : clock synchronous serial i/o mode 0 1 0 : 0 1 1 : 1 0 0 : uart mode (transfer data length = 7 bits) 1 0 1 : uart mode (transfer data length = 8 bits) 1 1 0 : uart mode (transfer data length = 9 bits) 1 1 1 : do not select. b2 b1 b0 0 : internal clock 1 : external clock 0 : one stop bit 1 : two stop bits 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : sleep mode terminated (invalid) 1 : sleep mode selected do not select. bit name bit function at reset r/w undefined 7 to 0 uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) any value in the range from 00 16 to ff 16 can be set. assuming that the set value = n, brgi divides the count source frequency by (n + 1). wo b0 note: writing to this register must be performed while the transmission/reception halts. use the movm (movmb) or sta (stab, stad) instruction for writing to this register. b7 bit function at reset r/w uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) b0 note: use the movm (movmb) or sta (stab, stad) instruction for writing to this register. b7 b0 b7 (b15) (b8) transmit data is set. nothing is assigned. undefined undefined wo bit function at reset r/w reference 11-14 reference 11-11
7906 group user s manual rev.2.0 appendix 20-16 appendix 2. control registers uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) 0 1 2 3 4 5 6 7 brg count source select bits cts/rts function select bit (note 1) transmit register empty flag cts/rts enable bit uarti receive interrupt mode select bit clk polarity select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) transfer format select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : clock f 2 0 1 : clock f 16 1 0 : clock f 64 1 1 : clock f 512 0 : the cts function is selected. 1 : the rts function is selected. 0 : data is present in the transmit register. (transmission is in progress.) 1 : no data is present in the transmit register. (transmission is completed.) 0 : the cts/rts function is enabled. 1 : the cts/rts function is disabled. 0 : reception interrupt 1 : reception error interrupt 0 : at the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer clock, receive data is input. when not in transferring, pin clki s level is h. 1 : at the falling edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. when not in transferring, pin clki s level is l. 0 : lsb (least significant bit) first 1 : msb (most significant bit) first b1 b0 notes 1: valid when the cts/rts enable bit (bit 4) is 0 and cts i /rts i separate select bit (bit 0 or 1 at address ac 16 ) is 0. 2: fix these bits to 0 in the uart mode or when serial i/o is disabled. 0 0 0 1 0 0 0 0 rw rw rw ro rw rw rw rw bit name bit function at reset r/w uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) 0 1 2 3 4 5 6 7 transmit enable bit transmit buffer empty flag receive enable bit receive complete flag overrun error flag framing error flag (note) (valid in uart mode) parity error flag (note) (valid in uart mode) error sum flag (note) (valid in uart mode) b7 b6 b5 b4 b3 b2 b1 b0 0 : reception disabled 1 : reception enabled 0 : no data is present in the receive buffer register. 1 : data is present in the receive buffer register. note: bits 5 to 7 are invalid in the clock synchronous serial i/o mode. 0 : transmission disabled 1 : transmission enabled 0 : data is present in the transmit buffer register. 1 : no data is present in the transmit buffer register. 0 : no parity error 1 : parity error detected 0 : no error 1 : error detected 0 : no overrun error 1 : overrun error detected 0 : no framing error 1 : framing error detected 0 1 0 0 0 0 0 0 rw ro rw ro ro ro ro ro bit name bit function at reset r/w reference 11-7 reference 11-9
7906 group user s manual rev.2.0 20-17 appendix appendix 2. control registers 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 count start register 0 (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : stop counting 1 : start counting bit name bit function at reset r/w reference 7-7 8-4 8 to 0 15 to 9 uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) b0 b7 b0 b7 (b15) (b8) receive data is read out from here. the value is 0 at reading. undefined 0 ro bit function at reset r/w reference 11-13 0 0 0 0 0 undefined 0 1 2 3 4 7 to 5 count start register 1 (address 41 16 ) timer a5 count start bit timer a6 count start bit timer a7 count start bit timer a8 count start bit timer a9 count start bit nothing is assigned. rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : stop counting 1 : start counting bit name bit function at reset r/w reference 7-7
7906 group user s manual rev.2.0 appendix 20-18 appendix 2. control registers 0 1 2 3 4 6, 5 7 wo wo wo wo wo rw 0 0 0 0 0 undefined 0 one-shot start register 0 (address 42 16 ) b7 b6 b5 b4 b3 b2 b1 b0 1 : start outputting one-shot pulse. (valid when an internal trigger is selected.) the value is 0 at reading. 0 timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit fix this bit to 0. timer a4 one-shot start bit nothing is assigned. fix this bit to 0. bit name bit function at reset r/w reference 7-33 1 : start outputting one-shot pulse. (valid when an internal trigger is selected.) the value is 0 at reading. 3 to 0 4 6, 5 7 wo wo rw 0 0 undefined 0 one-shot start register 1 (address 43 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 fix these bits to 000. timer a9 one-shot start bit nothing is assigned. fix this bit to 0. bit name bit function at reset r/w reference 7-33 1 : start outputting one-shot pulse. (valid when an internal trigger is selected.) the value is 0 at reading. 0 0000
7906 group user s manual rev.2.0 20-19 appendix appendix 2. control registers b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 up-down register 0 (address 44 16 ) timer a0 up-down bit timer a1 up-down bit timer a2 up-down bit fix this bit to 0. timer a4 up-down bit timer a2 two-phase pulse signal processing select bit fix this bit to 0. timer a4 two-phase pulse signal processing select bit 0 : countdown 1 : countup this function is valid when the contents of the up- down register is selected as the up-down switching factor. 0 : countdown 1 : countup this function is valid when the contents of the up- down register is selected as the up-down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, clear the bit to 0. the value is 0 at reading. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, clear the bit to 0. the value is 0 at reading. 0 0 0 0 0 0 0 0 rw rw rw rw rw wo (note) wo (note) wo (note) note: use the movm (movmb) or sta(stab, stad) instruction for writing to bits 5 to 7. bit name bit function at reset r/w reference 7-24 7-24 7-26 7-26 00 b7 b6 b5 b4 b3 b2 b1 b0 3 to 0 4 6, 5 7 up-down register 1 (address c4 16 ) fix these bits to 0000. timer a9 up-down bit fix these bits to 00. timer a9 two-phase pulse signal processing select bit 0 : countdown 1 : countup this function is valid when the contents of the up- down register is selected as the up-down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, clear the bit to 0. the value is 0 at reading. 0 0 0 0 rw rw wo (note) wo (note) note: use the movm(movmb) or sta(stab, stad) instruction for writing to bits 5 to 7. bit name bit function at reset r/w reference 7-24 7-26 00 000 0
7906 group user s manual rev.2.0 appendix 20-20 appendix 2. control registers 0 1 7 to 2 timer a clock division select register (address 45 16 ) timer a clock division select bits the value is 0 at reading. 0 0 0 rw rw b7 b6 b5 b4 b3 b2 b1 b0 see table 7.2.3. bit name bit function at reset r/w timer a0 register (addresses 47 16 , 46 16 ) timer a5 register (addresses c7 16 , c6 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a6 register (addresses c9 16 , c8 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a7 register (addresses cb 16 , ca 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a8 register (addresses cd 16 , cc 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined 15 to 0 these bits have different functions according to the operating mode. rw b0 b7 b0 b7 (b15) (b8) note: reading from or writing to this register must be performed in a unit of 16 bits. bit function at reset r/w operating mode select bits (note) these bits have different functions according to the operating mode. 0 1 2 3 4 5 6 7 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) timer ai mode register (i = 5 to 9) (addresses d6 16 to da 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot pulse mode 1 1 : pulse width modulation (pwm) mode. b1 b0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw bit name bit function at reset r/w reference 7-6 reference 7-5 reference 7-8 note: for timers a3 and a5 to a8, fix these bits to 00 ; do not select 01 2 , 10 2 , and 11 2 .
7906 group user s manual rev.2.0 20-21 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 timer a0 register (addresses 47 16 , 46 16 ) timer a5 register (addresses c7 16 , c6 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a6 register (addresses c9 16 , c8 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a7 register (addresses cb 16 , ca 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a8 register (addresses cd 16 , cc 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined 15 to 0 any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. rw b0 b7 b0 b7 (b15) (b8) timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits pulse output function select bit gate function select bits fix this bit to 0 in timer mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 00 0 0 : no gate function 0 1 : (taj in pin functions as a programmable i/o port pin.) 1 0 : gate function (counter is active only while taj in pin s in- put signal is at l level.) 1 1 : gate function (counter is active only while taj in pin s in- put signal is at h level.) b4 b3 0 : no pulse output (taj out pin functions as a programmable i/o port pin.) 1 : pulse output (taj out pin functions as a pulse output pin.) 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw see table 7.2.3. 0 note: reading from or writing to this register must be performed in a unit of 16 bits. bit name bit function at reset r/w bit function at reset r/w timer mode reference 7-12 reference 7-12 9-11 10-14 7-16 7-15 7-6 0 1 5 to 2 6 7 timer ak mode register (k = 3, 5 to 8) (addresses 59 16 , d6 16 to d9 16 ) operating mode select bits fix these bits to 0000 in timer mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 00 0 0 0 0 0 rw rw rw rw rw see table 7.2.3. 0 bit name bit function at reset r/w reference 7-12 9-11 7-6 00 0
7906 group user s manual rev.2.0 appendix 20-22 appendix 2. control registers 0 1 2 3 4 5 6 7 event counter mode rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 15 to 0 rw b0 b7 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) b0 b7 (b15) (b8) timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits pulse output function select bit count polarity select bit up-down switching factor select bit fix this bit to 0 in event counter mode. these bits are invalid in event counter mode. b7 b6 b5 b4 b3 b2 b1 b0 0 1 : event counter mode b1 b0 01 0 : no pulse output (taj out pin functions as a programmable i/o port pin.) 1 : pulse output (taj out pin functions as a pulse output pin.) x : it may be either 0 or 1. xx 0 0 : counts at falling edge of external signal 1 : counts at rising edge of external signal 0 : contents of up-down register 1 : input signal to taj out pin bit function at reset r/w bit name bit function at reset r/w undefined any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (ffff 16 n + 1) during countup. when reading, the register indicates the counter value. note: reading from or writing to this register must be performed in a unit of 16 bits. reference 7-20 reference 7-20 7-26 7-20 7-24
7906 group user? manual rev.2.0 20-23 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 one-shot pulse mode rw rw rw rw rw rw rw rw timer aj mode register (j = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits fix this bit to ??in one-shot pulse mode. trigger select bits fix this bit to ??in one-shot pulse mode. count source select bits b7 b6 b5 b4 b3 b2 b1 b0 1 0 : one-shot pulse mode b1 b0 10 0 0 0 : writing ??to one-shot start bit 0 1 : (taj in pin functions as a programmable i/o port pin.) 1 0 : falling edge of taj in pin? input signal 1 1 : rising edge of taj in pin? input signal b4 b3 1 0 0 0 0 0 0 0 0 see table 7.2.3. undefined 15 to 0 any value in the range from ?000 16 ?to ?fff 16 ?can be set. assuming that the set value = n, the ??level width of the one-shot pulse which is output from the taj out pin is expressed as follows : wo b0 b7 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) b0 b7 (b15) (b8) f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. n f i . bit function at reset r/w bit name bit function at reset r/w reference 7-30 10-13 reference 7-30 10-13 7-33 7-6
7906 group user? manual rev.2.0 appendix 20-24 appendix 2. control registers rw rw rw rw rw rw rw rw pulse width modulation (pwm) mode 0 1 2 3 4 5 6 7 timer aj mode register (i = 0 to 2, 4, 9) (addresses 56 16 to 58 16 , 5a 16 , da 16 ) operating mode select bits fix this bit to ??in pwm mode. trigger select bits 16/8-bit pwm mode select bit count source select bits b7 b6 b5 b4 b3 b2 b1 b0 1 1 : pwm mode b1 b0 11 0 0 : writing ??to count start bit 0 1 : (taj in pin functions as a programmable i/o port pin.) 1 0 : falling edge of taj in pin? input signal 1 1 : rising edge of taj in pin? input signal b4 b3 1 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 0 0 0 0 0 0 0 see table 7.2.3. timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined 15 to 0 any value in the range from ?000 16 ?to ?ffe 16 ?can be set. assuming that the set value = n, the ??level width of the pwm pulse which is output from the taj out pin is expressed as follows : (pwm pulse period = ) wo b0 b7 b0 b7 (b15) (b8) f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. n f i 2 16 ? f i timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) timer a9 register (addresses cf 16 , ce 16 ) undefined undefined 7 to 0 15 to 8 any value in the range from ?0 16 ?to ?f 16 ?can be set. assuming that the set value = m, the period of the pwm pulse which is output from the taj out pin is expressed as follows: wo wo b0 b7 b0 b7 (b15) (b8) (m + 1) (2 8 ?1) f i any value in the range from ?0 16 ?to ?f 16 ?can be set. assuming that the set value = n, the ??level width of the pwm pulse which is output from the taj out pin is expressed as follows: n(m + 1) f i f i : frequency of count source note: use the movm or sta(stad) instruction for writing to this register. writing to this register must be performed in a unit of 16 bits. bit function at reset r/w bit name bit function at reset r/w bit function at reset r/w reference 7-39 reference 7-39 9-11 7-42 7-43 7-6 reference 7-39
7906 group user? manual rev.2.0 20-25 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 reference 8-3 reference 8-4 undefined 15 to 0 these bits have different functions according to the operating mode. rw b0 b7 b0 b7 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) note: reading from or writing to this register must be performed in a unit of 16 bits. bit function at reset r/w operating mode select bits these bits have different functions according to the operating mode. timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : do not select. b1 b0 note: bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. 0 0 0 0 0 undefined 0 0 rw rw rw rw rw ro (note) rw rw bit name bit function at reset r/w
7906 group user? manual rev.2.0 appendix 20-26 appendix 2. control registers 0 1 2 3 4 5 6 7 timer mode operating mode select bits these bits are invalid in timer mode. this bit is invalid in timer mode; its value is undefined at reading. count source select bits undefined 15 to 0 any value in the range from ?000 16 ?to ?fff 16 ?can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. rw b0 b7 b0 b7 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 00 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 x : it may be either ??or ?. xx x 0 0 0 0 0 undefined 0 0 rw rw rw rw rw ro rw rw note: reading from or writing to this register must be performed in a unit of 16 bits. bit function at reset r/w bit name bit function at reset r/w reference 8-9 reference 8-9 8-7 x
7906 group user? manual rev.2.0 20-27 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 event counter mode operating mode select bits count polarity select bits this bit is invalid in event counter mode. this bit is invalid in event counter mode; its value is undefined at reading. these bits are invalid in event counter mode. rw rw rw rw rw ro rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 1 : event counter mode b1 b0 01 0 0 : count at falling edge of external signal 0 1 : count at rising edge of external signal 1 0 : count at both falling and rising edges of external signal 1 1 : do not select. (note) b3 b2 x : it may be either ??or ?. note: when the timer b2 clock source select bit (bit 6 at address 63 16 ) = ?,?be sure to fix these bits to ?1 2 ?(count at the rising edge of the external signal). x xx 0 0 0 0 0 undefined 0 0 bit name bit function at reset r/w undefined 15 to 0 any value in the range from ?000 16 ?to ?fff 16 ?can be set. assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. rw b0 b7 b0 b7 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) note: reading from or writing to this register must be performed in a unit of 16 bits. bit function at reset r/w reference 8-14 reference 8-14 x
7906 group user? manual rev.2.0 appendix 20-28 appendix 2. control registers 0 1 2 3 4 5 6 7 pulse period/pulse width measurement mode note: reading from this register must be performed in a unit of 16 bits. undefined 15 to 0 the measurement result of pulse period or pulse width is read out. ro timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) operating mode select bits measurement mode select bits count-type select bit timer bi overflow flag (note) count source select bits b7 b6 b5 b4 b3 b2 b1 b0 1 0 : pulse period/pulse width measurement mode b1 b0 10 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement (interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : do not select. b3 b2 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 note: the timer bi overflow flag is cleared to ??when a value is written to the timer bi mode register with the count start bit = 1. this flag cannot be set to ??by software. 0 : no overflow 1 : overflowed 0 0 0 0 0 undefined 0 0 rw rw rw rw rw ro rw rw b0 b7 b0 b7 (b15) (b8) bit function at reset r/w bit name bit function at reset r/w reference 8-21 reference 8-21 8-23 8-24 8-7 0 : counter clear type 1 : free-run type
7906 group user? manual rev.2.0 20-29 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 bit name bit processor mode register 0 (address 5e 16 ) function at reset r/w processor mode bits interrupt priority detection time select bits software reset bit fix this bit to ?. b7 b6 b5 b4 b3 b2 b1 b0 0 0 : single-chip mode 0 1 : do not select. 1 0 : do not select. 1 1 : do not select. b1 b0 0 0 : 7 cycles of f sys 0 1 : 4 cycles of f sys 1 0 : 2 cycles of f sys 1 1 : do not select. b5 b4 the microcomputer is reset by writing ??to this bit. the value is ??at reading. 0 0 0 1 0 0 0 0 rw rw rw rw rw rw wo rw reference 2-20 6-12 3-3 0xx 0 0 any of these bits may be either ??or ?. x : it may be either ??or ?. 0 1 6 to 2 7 rw rw rw rw 1 0 0 0 processor mode register 1 (address 5f 16 ) bit name bit function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 : only dpr0 is used. 1 : dpr0 through dpr3 are used. 0 : 3 1 : 2 (note 1) this bit may be either ??or ?. direct page register switch bit fix these bits to ?0000. internal rom bus cycle select bit (note 2) x : it may be either ??or ?. notes 1: after reset, this bit is allowed to be changed only once. (during the software execution, be sure not to change this bits content.) 2: to reprogram the internal flash memory by using the cpu reprogramming mode, clear this bit to ?.?(refer to section ?9.2 flash memory cpu reprogramming mode. ) reference 2-6 2-12 x 0 0000
7906 group user? manual rev.2.0 appendix 20-30 appendix 2. control registers 0 5 to 1 6 7 undefined 7 to 0 initializes the watchdog timer. when dummy data has been written to this register, the watchdog timer? value is initialized to ?ff 16 ?(dummy data: 00 16 to ff 16 ). b0 b7 watchdog timer register (address 60 16 ) bit function at reset r/w rw rw rw bit name bit watchdog timer frequency select register (address 61 16 ) function at reset r/w watchdog timer frequency select bit nothing is assigned. watchdog timer clock source select bits at stp termination 0 undefined 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 : wf 512 1 : wf 32 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 b7 b6 reference 14-3 reference 14-3 14-3 15-7
7906 group user? manual rev.2.0 20-31 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 0 1 7 to 2 rw (note) rw (note) rw 0 0 0 bit name bit particular function select register 0 (address 62 16 ) function at reset r/w stp instruction invalidity select bit external clcok input select bit fix these bits to ?00000. b7 b6 b5 b4 b3 b2 b1 b0 0 : stp instruction is valid. 1 : stp instruction is invalid. 0 : oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1 : oscillation circuit is inactive. (external clock is input.) when the system clock select bit (bit 5 at address bc 16 ) = ?, watchdog timer is not used at stop mode termination. when the system clock select bit = ?, watchdog timer is used at stop mode termination. 00 0 00 0 note: writing to these bits requires the following procedure: ?write ?5 16 ?to this register. (the bit status does not change only by this writing.) ?succeedingly, write ??or ??to each bit. also, use the movmb ( movm when m = 1) instruction or stab ( sta when m = 1) instruction. if an interrupt occurs between writing of ?5 16 ?and next writing of ??or ?,?latter writing may be ignored. when there is a possibility that an interrupt occurs at the above timing, be sure to read this bits contents after writing of ??or ?,?and verify whether ??or ??has correctly been written or not. rw (note 2) rw (note 2) rw rw rw rw notes 1: at power-on reset, this bit becomes ?.?at hardware reset or software reset, this bit retains the value just before reset. 2: even when ??is written, the bit status will not change. 3: setting this bit to ??must be performed just before execution of the wit instruction. also, after the wait state is termi- nated, this bit must be cleared to ??immediately. (note 1) (note 1) 0 0 0 0 0 0 particular function select register 1 (address 63 16 ) b7 b6 b5 b4 b3 b2 b1 b0 bit name bit function at reset r/w stp-instruction-execution status bit wit-instruction-execution status bit fix this bit to ?. system clock stop select bit at wit (note 3) fix this bit to ?. the value is ??at reading. timer b2 clock source select bit (valid in event counter mode.) the value is ??at reading. 0 : normal operation. 1 : during execution of stp instruction 0 : normal operation. 1 : during execution of wit instruction 0 : external signal input to the tb2 in pin is counted. 1 : fx 32 is counted. 0 : in the wait mode, system clock f sys is active. 1 : in the wait mode, system clock f sys is inactive. reference 15-4 4-10 15-5 16-4 reference 15-6 16-5 8-15 00
7906 group user? manual rev.2.0 appendix 20-32 appendix 2. control registers undefined 7 to 0 bit function at reset r/w disables the watchdog timer. when values of ?9 16 ?and ?0 16 ?succeedingly in this order, the watchdog timer will stop its operation. b0 b7 particular function select register 2 (address 64 16 ) note: after reset, this register can be set only once. writing to this register requires the following procedure: ?write values of ?9 16 ?and ?0 16 ?to this register succeedingly in this order. ?for the above writing, be sure to use the movmb ( movm when m = 1) instruction or the stab ( sta when m = 1). note that the following: if an interrupt occurs between writing of ?9 16 ?and next writing of ?0 16 ,?the watchdog timer does not stop its operation. if any of the following has been performed after reset, writing to this register will be disabled from that time: ?if this register is read out. ?if writing to this register is performed by the procedure other than the above procedure. reference 14-4
7906 group user? manual rev.2.0 20-33 appendix appendix 2. control registers 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 notes 1: these bits are valid when the detect enable bit (bit 5) = ?.?therefore, these bits must be set before or simultaneously with setting of the detect enable bit to ?. 2: at power-on reset, each bit becomes ?? at hardware reset or software reset, each bit retains the value immediately before reset. bit name bit debug control register 0 (address 66 16 ) function detect condition select bits (note 1) fix these bits to ?0. detect enable bit fix this bit to ?. the value is ? at reading. rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : do not select. 0 0 1 : address matching detection 0 0 1 0 : address matching detection 1 0 1 1 : address matching detection 2 1 0 0 : do not select. 1 0 1 : out-of-address-area detection 1 1 0 : 1 1 1 : b2 b1 b0 0 : detection disabled. 1 : detection enabled. (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) 1 do not select. 000 at reset r/w (note 1) (note 1) 0 0 undefined 0 0 0 rw ro rw rw ro ro bit name bit debug control register 1 (address 67 16 ) function at reset r/w fix this bit to ?. the value is ??at reading. address compare register access enable bit (note 2) fix this bit to ??when using the debug function. nothing is assigned. while a debugger is not used, the value is ??at reading. while a debugger is used, the value is ??at reading. address-matching-detection 2 decision bit (valid when the address match- ing detection 2 is selected.) the value is ??at reading. 0 0 : disabled. 1 : enabled. 0 : matches with the contents of the address com- pare register 0. 1 : matches with the contents of the address com- pare register 1. 1 notes 1: at power-on reset, each bit becomes ?? at hardware reset or software reset, each bit retains the value immediately before res et. 2: be sure to set this bit to ??immediately before the access to the address compare registers 0 and 1 (addresses 68 16 to 6d 16 ). then, be sure to clear this bit to ??immediately after this access. b7 b6 b5 b4 b3 b2 b1 b0 address compare register 0 (addresses 6a 16 to 68 16 ) address compare register 1 (addresses 6d 16 to 6b 16 ) undefined 23 to 0 bit function at reset r/w the address to be detected (in other words, the start address of instructions) is set here. rw b0 b7 b7 b0 b7 (b23) (b8) (b15) (b16) b0 note: when accessing these registers, be sure to set the address compare register access enable bit (bit 2 at address 67 16 ) to ? immediately before this access. then, be sure to clear this bit to ??immediately after this access. reference 17-3 reference 17-4 reference 17-5
7906 group user? manual rev.2.0 appendix 20-34 appendix 2. control registers 0 1 2 3 7 to 4 a-d conversion, uart0 and 1 transmit, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 70 16 to 7c 16 ) timers a5 to a9 interrupt control registers (addresses f5 16 to f9 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt priority level select bits interrupt request bit nothing is assigned. notes 1: the a-d conversion interrupt request bit is undefined after reset. 2: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 0 0 0 (note 1) undefined rw rw rw rw (note 2) bit name bit function at reset r/w reference 6-7 timer ai 7-9 timer bi 8-5 uart0 uart1 11-15 a-d 12-10 0 1 2 3 4 5 7, 6 int 3 to int 7 interrupt control registers (addresses 6e 16 , 6f 16 , fd 16 , fe 16 , ff 16 ) interrupt priority level select bits interrupt request bit (note 1) polarity select bit level sense/edge sense select bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 notes 1: the interrupt request bits of int 3 to int 7 interrupts are invalid when the level sense is selected. 2: when writing to this bit, use the movm (movmb) or sta (stab, stad) instruction. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested 0 : the interrupt request bit is set to ??at ??level when level sense is selected; this bit is set to ? at falling edge when edge sense is selected. 1 : the interrupt request bit is set to ??at ??level when level sense is selected; this bit is set to ? at rising edge when edge sense is selected. 0 : edge sense 1 : level sense 0 0 0 0 0 0 undefined rw rw rw rw (note 2) rw rw bit name bit function at reset r/w reference 6-7 6-18
7906 group user? manual rev.2.0 20-35 appendix appendix 2. control registers 2 to 0 3 4 5 6 7 0 1 7 to 2 bit name bit function at reset r/w external interrupt input read register (address 95 16 ) the value is undefined at reading. int 3 read out bit int 4 read out bit int 5 read out bit int 6 read out bit int 7 read out bit undefined undefined undefined undefined undefined undefined ro ro ro ro ro ro b7 b6 b5 b4 b3 b2 b1 b0 the input level at the corresponding pin is read out. 0 : ??level 1 : ??level bit name bit function at reset r/w d-a 0 output enable bit d-a 1 output enable bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 0: output is disabled. 1: output is enabled. (notes 1, 2) 0: output is disabled. 1: output is enabled. (notes 1, 2) 0 0 undefined rw rw d-a control register (address 96 16 ) notes 1: pin da i is multiplexed with an analog input pin, external interrupt input pin, and trigger input pin in the pulse output port mode. when a d-a i output enable bit = ??(in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/output pin (including a programmable i/o port pin). 2: when not using the d-a converter, be sure to clear this bit to ?. 0 7 to 0 bit d-a register i (i = 0 and 1) (addresses 98 16 and 99 16 ) function at reset r/w any value in the range from 00 16 through ff 16 can be set (note) , and this value will be d-a converted and will be output. rw b0 b7 reference 6-18 reference 13-3 reference 13-3 note: when not using the d-a converter, be sure to clear the contents of these bits to ?0 16 .
7906 group user? manual rev.2.0 appendix 20-36 appendix 2. control registers 0 1 2 3 4 5 7, 6 ry/by status bit cpu reprogramming mode select bit the value is ??at reading. flash memory reset bit (note 3) the value is ??at reading. user rom area select bit (valid in boot mode) (note 5) the value is ??at reading. ro rw (notes 1, 2) rw (note 4) rw (note 2) 1 0 0 0 0 0 0 bit name bit flash memory control register (address 9e 16 ) function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 : busy (automatic programming or erase operation is active.) 1 : ready (automatic programming or erase operation has been completed.) 0 : flash memory cpu reprogramming mode is invalid. 1 : flash memory cpu reprogramming mode is valid. notes 1: in order to set this bit to ?,?write ??followed with ??successively; while in order to clear this bit ?,?write ?. 2: writing to this bit must be performed in an area other than the internal flash memory. 3: this bit is valid when the cpu reprogramming mode select bit (bit 1) = ?? on the other hand, when the cpu reprogramming mode select bit = ?,?be sure to fix this bit to ?.?rewriting of this bit must be performed with the cpu reprogramming mode select bit = ?. 4: after writing of ??to this bit, be sure to confirm the ry/by status bit (bit 0) becomes ?? and then, write ??to this bit. 5: when md1 = vss level, this bit is invalid. (it may be either 0?or ?.? 0 : access to boot rom area 1 : access to user rom area writing ??into this bit discontinues the access to the internal flash memory. this causes the built-in flash memory circuit being reset. reference 19-10 19-11
7906 group user? manual rev.2.0 20-37 appendix appendix 2. control registers waveform output mode register (address a6 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 x 0 1 2 3 4 5 6 7 waveform output select bits (note) pulse output mode select bit pulse width modulation timer select bit waveform output control bit 0 waveform output control bit 1 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 bit name bit waveform output mode register (address a6 16 ) function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 when pulse mode 0 is selected, 0: rtp1 0 , rtp1 1 : pulse outputs are disabled. 1: rtp1 0 , rtp1 1 : pulse outputs are enabled. when pulse mode 1 is selected, fix this bit to ?. see table 9.2.1. see table 9.2.2. 0 : pulse mode 0 1 : pulse mode 1 when pulse mode 0 is selected, 0 : rtp0 0 to rtp0 3 : pulse outputs are disabled. 1 : rtp0 0 to rtp0 3 : pulse outputs are enabled. when pulse mode 1 is selected, 0 : rtp0 0 to rtp0 3 rtp1 0 , rtp1 1 : pulse outputs are disabled. 1 : rtp0 0 to rtp0 3 rtp1 0 , rtp1 1 : pulse outputs are enabled. waveform output mode register (address a6 16 ) three-phase waveform mode pulse output mode reference 10-6 reference 9-4 9-5 waveform output select bits (note 1) three-phase output polarity set buffer (valid in three-phase mode 1) (note 2) three-phase mode select bit dead-time timer trigger select bit (note 3) waveform output control bit bit name bit function at reset r/w rw rw rw rw rw rw rw rw x: it may be either ??or ?. notes 1: when not using the pulse output mode and three-phase waveform mode, be sure to fix these bits to ?00 2 . 2: this bit is invalid in three-phase mode 0. 3: when the saw-tooth-wave modulation output is performed, be sure to fix this bit to ?. 4: writing to any of bits 0 to 6 must be performed while counting for timers a0 to a3 halts. 1 0 0 : three-phase waveform mode 0 : ??output 1 : ??output 0 : three-phase mode 0 1 : three-phase mode 1 0: both falling and rising edges of one-shot pulse for timers a0 to a2 1: only the falling edge of one-shot pulse for timers a0 to a2 0 : waveform output disabled 1 : waveform output enabled b0 b2 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 note: when not using the pulse output port mode and three-phase waveform mode, be sure to fix these bits to ?00 2 . invalid in the three-phase waveform mode. b1
7906 group user? manual rev.2.0 appendix 20-38 appendix 2. control registers reference 10-7 undefined 7 to 0 bit dead-time timer (address a7 16 ) function at reset r/w a value in the range from ?0 16 ?to ?f 16 ?can be set. wo b0 b7 note: use the movmb ( movm when m = 1) or stab ( sta when m = 1) instruction for writing to this register. additionally, make sure writing to this register does not overlap with a trigger-occurrence timing of the dead-time timer.
7906 group user? manual rev.2.0 20-39 appendix appendix 2. control registers three-phase output data register 0 (address a8 16 ) three-phase waveform mode 10-9 reference 9-7 three-phase output data register 0 (address a8 16 ) b7 b6 b5 b4 b3 b2 b1 b0 x reference x 0 1 2 3 4 5 7, 6 rw rw rw rw rw rw rw 0 0 0 0 0 0 0 bit name bit three-phase output data register 0 (address a8 16 ) function at reset r/w b7 b6 b5 b4 b3 b2 b1 b0 0 : ??level output 1 : ??level output note: invalid in pulse mode 0. rtp0 0 pulse output data bit rtp0 1 pulse output data bit rtp0 2 pulse output data bit rtp0 3 pulse output data bit rtp1 0 pulse output data bit (valid in pulse mode 1.) (note) rtp1 1 pulse output data bit (valid in pulse mode 1.) (note) pulse output trigger select bits 0 : ??level output 1 : ??level output 0 0 : underflow of timer a0 0 1 : falling edge of input signal to pin rtp trg0 1 0 : rising edge of input signal to pin rtp trg0 1 1 : both falling and rising edges of input signal to pin rtp trg0 b7 b6 x: it may be either ??or ?. note: this bit is invalid in three-phase mode 1. 0 0 : f 2 0 1 : f 2 /2 1 0 : f 2 /4 1 1 : do not select. w-phase output fix bit v-phase output fix bit u-phase output fix bit w-phase output polarity set buffer (valid in three-phase mode 0.) (note) clock-source-of-dead-time-timer select bits bit name bit 0 1 2 3 5, 4 6 7 function at reset r/w 0 0 0 0 0 0 0 rw rw rw rw rw rw rw 0 : released from output fixation 1 : output fixed 0 : released from output fixation 1 : output fixed 0 : released from output fixation 1 : output fixed b7 b6 0 : ??output 1 : ??output pulse output port mode invalid in the three-phase waveform mode.
7906 group user? manual rev.2.0 appendix 20-40 appendix 2. control registers three-phase output data register 1 (address a9 16 ) three-phase output data register 1 (address a9 16 ) three-phase waveform mode pulse output port mode pulse width modulation enable bit 0 pulse width modulation enable bit 1 pulse width modulation enable bit 2 pulse output polarity select bit rtp1 0 pulse output data bit (valid in pulse mode 0) (note) rtp1 1 pulse output data bit (valid in pulse mode 0) (note) x 0 1 2 3 4 5 6 7 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 bit name bit function at reset r/w 0 : positive 1 : negative 0 : no pulse width modulation by timer a1 1 : pulse width modulation by timer a1 b7 b6 b5 b4 b3 b2 b1 b0 0 : no pulse width modulation by timer a2 1 : pulse width modulation by timer a2 0 : no pulse width modulation by timer a4 1 : pulse width modulation by timer a4 0 : ??level output 1 : ??level output x x: it may be either ??or ?. note: invalid in pulse mode 1. reference 10-11 reference 9-7 three-phase output data register 1 (address a9 16 ) b7 b6 b5 b4 b3 b2 b1 b0 x x 0 : ??output 1 : ??output 0 : an interrupt request occurs at each even-number- ed underflow of timer a3 1 : an interrupt request occurs at each odd-number- ed underflow of timer a3 w-phase fixed outputs polarity set bit (note 1) v-phase fixed outputs polarity set bit (note 2) u-phase fixed outputs polarity set bit (note 3) v-phase output polarity set buffer (in three-phase mode 0) interrupt request interval set bit (in three-phase mode 1) u-phase output polarity set buffer (in three-phase mode 0) interrupt validity output select bit (in three-phase mode 1) 0 : ??output 1 : ??output 0 : every second time 1 : every forth time bit name bit 0 1 2 3 4 5 7, 6 function at reset r/w 0 : ??output fixed 1 : ??output fixed 0 : ??output fixed 1 : ??output fixed 0 : ??output fixed 1 : ??output fixed 0 0 0 0 0 0 0 rw rw rw rw rw rw rw x: it may be either ??or ?. notes 1: valid when the w-phase output fix bit (bit 0 at address a8 16 ) = ?.?be sure not to change the value during output of a fixed value. 2: valid when the v-phase output fix bit (bit 1 at address a8 16 ) = ?.?be sure not to change the value during output of a fixed value. 3: valid when the u-phase output fix bit (bit 2 at address a8 16 ) = ?.?be sure not to change the value during output of a fixed value. x invalid in the three-phase waveform mode. invalid in the three-phase waveform mode. invalid in pulse output port mode.
7906 group user? manual rev.2.0 20-41 appendix appendix 2. control registers note: this register is valid only in the three-phase mode. bit name bit 0 1 2 3 7 to 4 position-data-retain function control register (address aa 16 ) function at reset r/w w-phase position data retain bit v-phase position data retain bit u-phase position data retain bit retain-trigger polarity select bit nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 undefined ro ro ro rw input level at pin idw is read out. 0 : ??level 1 : ??level input level at pin idv is read out. 0 : ??level 1 : ??level input level at pin idu is read out. 0 : ??level 1 : ??level 0 : falling edge of positive phase 1 : rising edge of positive phase reference 10-12 serial i/o pin control register (address ac 16 ) b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 7 to 4 cts 0 /rts 0 separate select bit (note) cts 1 /rts 1 separate select bit (note) txd 0 /p1 3 switch bit txd 1 /p1 7 switch bit the value is ?000?at reading. 0 : cts 0 /rts 0 are used together. 1 : cts 0 /rts 0 are separated. 0 : functions as txd 1 . 1 : functions as p1 7 . rw rw rw rw bit name bit function at reset r/w 0 : cts 1 /rts 1 are used together. 1 : cts 1 /rts 1 are separated. 0 : functions as txd 0 . 1 : functions as p1 3 . 0 0 0 0 0 reference 11-17 note: valid when the cts/rts enable bit (bit 4 at addresses 34 16 and 3c 16 ) is ?.
7906 group user? manual rev.2.0 appendix 20-42 appendix 2. control registers 0 1 2 3 4 5 6 7 1 1 1 0 1 0 0 0 clock control register 0 (address bc 16 ) bit name bit function at reset r/w fix this bit to ?. pll circuit operation enable bit (note 1) pll multiplication ratio select bits (note 2) fix this bit to ?. system clock select bit (note 3) peripheral device? clock select bit 0 peripheral device? clock select bit 1 b7 b6 b5 b4 b3 b2 b1 b0 0 : pll frequency multiplier is inactive, and pin v cont is invalid. (floating) 1 : pll frequency multiplier is active, and pin v cont is valid. 0 0 : do not select. 0 1 : ? 2 1 0 : ? 3 1 1 : ? 4 b3 b2 see table 4.2.2. 0 : fx in 1 : f pll 1 1 rw rw rw rw rw rw rw rw reference 4-6 4-7 notes 1: clear this bit to ??if the pll frequency multiplier needs not to be active. in the stop and flash memory parallel i/o modes, the pll frequency multiplier is inactive and pin v cont is invalid regard- less of the contents of this bit. 2: rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to ?. then, set bit 5 to ??2 ms after the rewriting of these bits. (after reset, these bits are allowed to be changed only once.) 3: clearance of the pll circuit operation enable bit (bit 1) to ??clears the system clock select bit to ?.?also, while the pl l circuit operation enable bit = ?,?nothing can be written to the system clock select bit. (fixed to be ?.? before setting of the system clock select bit to ??after reset, it is necessary to insert an interval of 2 ms after the stabilization of f(x in ). port p2 pin function control register (address ae 16 ) 0 1 2 3 6 to 4 7 bit name bit function at reset r/w pin tb0 in select bit pin tb1 in select bit pin tb2 in select bit pin int 3 /rtp trg0 select bit (note) nothing is assigned. fix this bit to ?. b7 b6 b5 b4 b3 b2 b1 b0 0 : allocate pin tb2 in to p5 7 . 1 : allocate pin tb2 in to p2 6 . 0: allocate pin int 3 /rtp trg0 to p7 4 . 1: allocate pin int 3 /rtp trg0 to p2 7 . 0 : allocate pin tb0 in to p5 5 . 1 : allocate pin tb0 in to p2 4 . 0 : allocate pin tb1 in to p5 6 . 1 : allocate pin tb1 in to p2 5 . 0 0 0 0 undefined 0 rw rw rw rw rw reference 6-18 8-6 9-9 note: when allocating pin int 3 /rtp trg0 to p7 4 , be sure the d-a 1 output enable bit (bit 1 at address 96 16 ) = ??(output disabled). 0
7906 group user? manual rev.2.0 20-43 appendix appendix 2. control registers timer a0 1 register (addresses d1 16 , d0 16 ) timer a1 1 register (addresses d3 16 , d2 16 ) timer a2 1 register (addresses d5 16 , d4 16 ) b0 b7 b0 b7 (b15) (b8) reference 10-13 undefined 15 to 0 bit function at reset r/w any value in the range from 0000 16 to ffff 16 can be set. assuming that the set value = n, the ??level width of the one-shot pulse is expressed as follows: n/f i . wo f i : frequency of a count source notes 1: use the movm or sta (stad) instruction for writing to this register. additionally, make sure writing to this register must be performed in a unit of 16 bits. 2: this register is valid only in three-phase mode 1 of the three-phase waveform mode. bit name bit 0 1 2 3 4 7 to 5 comparator function select register 0 (address dc 16 ) function at reset r/w an 0 pin comparator function select bit an 1 pin comparator function select bit an 2 pin comparator function select bit an 3 pin comparator function select bit an 4 pin comparator function select bit fix these bits to ?00. 0 0 0 0 0 0 rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : the comparator function is not selected. 1 : the comparator function is selected. 00 0 note: writing to comparator function select register 0 must be performed while the a-d converter halts. bit name bit 0 1 2 3 4 7 to 5 comparator result register 0 (address de 16 ) function at reset r/w an 0 pin comparator result bit an 1 pin comparator result bit an 2 pin comparator result bit an 3 pin comparator result bit an 4 pin comparator result bit fix these bits to ?00. 0 0 0 0 0 0 rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 0 : the set value > the input level at pin an i 1 : the set value < the input level at pin an i 000 note: writing to comparator result register 0 must be performed while the a-d converter halts. reference 12-9 reference 12-9
appendix appendix 3. package outline 7906 group user? manual rev.2.0 20-44 appendix 3. package outline ssop42-p-450-0.80 weight(g) jedec code eiaj package code lead material cu alloy+42 alloy 42p2r-e plastic 42pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .25 0 .05 0 .13 0 .3 17 .2 8 .63 11 .3 0 .27 1 .0 2 .3 0 .15 0 .5 17 .4 8 .8 0 .93 11 .5 0 .765 1 .43 11 .4 2 .4 0 .2 0 .7 17 .6 8 .23 12 .7 0 .15 0 b 2 .5 0 0 10 e e 1 e b 2 e 1 i 2 recommended mount pad z 1 0.75 0.9 z 42 22 21 1 h e e e y f a a 2 a 1 l 1 l c detail f g b d detail g z z 1 sdip42-p-600-1.78 weight(g) jedec code 4.1 eiaj package code lead material alloy 42/cu alloy 42p4b plastic 42pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 3.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 1.778 15.24 3.0 0 15 5.5 e e 1 42 22 21 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d
appendix 7906 group user? manual rev.2.0 20-45 appendix 4. examples of handling unused pins appendix 4. examples of handling unused pins when unusing an i/o pin, some handling is necessary for this pin. examples of handling unused pins are described below. the following are just examples. in actual use, the user shall modify them according to the user? application and properly evaluate their performance. table 1 example of handling unused pins fig. 1 example of handling unused pins handling example set these pins to the input mode and connect each pin to vcc or vss via a resistor; or set these pins to the output mode and leave them open (note 1). connect this pin to vcc via a resistor. select a falling edge for pin int 4 . leave these pins open. connect this pin to vcc. connect these pins to vss. pin name p1, p2, p5 to p7 p6out cut /int 4 x out (note 2) , v cont (note 3) av cc av ss , v ref notes 1: when leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. therefore, voltage levels of these pins are undefined and the power source current may increase while these port pins are placed in the input mode. software reliability can be enhanced by setting the contents of the above ports?direction registers periodically. this is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. for unused pins, use the shortest possible wiring (within 20 mm from the microcomputer? pins). 2: this applies when a clock externally generated is input to pin x in . 3: be sure that the pll circuit operation enable bit (bit 1 at address bc 16 ) = ?. p1, p2, p5 to p7 m37906 left open left open left open v cc v cc v ss p1, p2, p5 to p7 m37906 av cc av ss v ref x out v cont av cc av ss v ref x out v cont v ss v cc v cc p6out cut /int 4 p6out cut /int 4 when setting port pins to input mode when setting port pins to output mode
appendix appendix 5. hexadecimal instruction code table 7906 group user? manual rev.2.0 20-46 appendix 5. hexadecimal instruction code table 0 123 456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1001 1 0 1 0 1 0 1 1 1100 1101 1 1 1 0 1111 d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 0 n o p i m p a s l a sec imp n e g a lda a,imm ldx abs l d a b a , a b s , x b p l r e l t a b l e 2 ldy dir rol a c l c i m p a b s a ldy abs table 3 c p x d i r p s h s t k s e i i m p e x t z a add a,imm l d x b i m m b m i r e l t a b l e 4 cpy dir pul stk c l i i m p e x t s a s u b a , i m m l d y b i m m b g t u r e l t a b l e 5 l s r a s e m i m p c l r b a cmp a,imm bbsb abs,b,rel b v c r e l t a b l e 6 b b c b d i r , b , r e l ror a c l r a o r a a , i m m bbcb abs,b,rel c l m i m p b l e u r e l t a b l e 7 c b e q b d i r / i m m , r e l p h d s t k clv imp x a b i m p a n d a , i m m bral rel bvs rel t a b l e 8 c b n e b d i r / i m m , r e l p l d s t k rti imp a s r a e o r a , i m m b g t r e l t a b l e 9 inc dir i n c a rts imp pha stk movm dir/imm inc abs b c c r e l table 10 d e c d i r d e c a r t l i m p pla stk m o v m a b s / i m m d e c a b s b c s r e l t a b l e 1 1 c b e q b a / i m m , r e l sep imm t x a i m p php stk stk/imm t a b l e 1 2 cbneb a/imm,rel clp imm t y a i m p plp stk c b e q a / i m m , r e l b l e r e l l d a a , a b s , x a d d a , a b s , x s u b a , a b s , x cmp a,abs,x o r a a , a b s , x a n d a , a b s , x eor a,abs,x clrmb dir s t x d i r ldad e,abs,x a d d d e , a b s , x subd e,abs,x cmpd e,abs,x stab a,abs,x sta a,abs,x s t a d e , a b s , x b g e r e l table 13 i n x i m p t a x i m p p h x s t k c l r m b a b s bne rel table 14 c l r m d i r i n y i m p t a y i m p p l x s t k l d x i m m clrm abs b l t r e l d e x i m p c l r x i m p phy stk cpx imm stx abs beq rel sty dir dey imp clry imp ply stk cpy imm sty abs b r k i m p ldx dir b b s b d i r , b , r e l c b n e a / i m m , r e l l d y i m m ldab a,abs l d a a , a b s add a,abs s u b a , a b s c m p a , a b s o r a a , a b s and a,abs e o r a , a b s l d a d e , a b s a d d d e , a b s s u b d e , a b s c m p d e , a b s s t a b a , a b s s t a a , a b s s t a d e , a b s l d a b a , a b l , x l d a a , a b l , x a d d d e , i m m subd e,imm m o v m b d i r / a b s , x movm dir/abs,x l d a d e , a b l , x j s r a b s j s r l a b l j s r ( a b s , x ) s t a b a , a b l , x s t a a , a b l , x s t a d e , a b l , x l d a b a , a b l l d a a , a b l l d a d e , i m m c m p d e , i m m m o v m b d i r / a b s m o v m d i r / a b s m o v m b a b s / a b s m o v m a b s / a b s ldad e,abl j m p a b s jmpl abl jmp (abs,x) s t a b a , a b l s t a a , a b l s t a d e , a b l l d a b a , d i r , x lda a,dir,x a d d a , d i r , x s u b a , d i r , x c m p a , d i r , x ora a,dir,x a n d a , d i r , x e o r a , d i r , x l d a d e , d i r , x addd e,dir,x s u b d e , d i r , x c m p d e , d i r , x stab a,dir,x sta a,dir,x stad e,dir,x l d a b a , d i r lda a,dir a d d a , d i r sub a,dir c m p a , d i r ora a,dir a n d a , d i r e o r a , d i r l d a d e , d i r addd e,dir s u b d e , d i r c m p d e , d i r s t a b a , d i r s t a a , d i r stad e,dir l d a b a , l ( d i r ) , y l d a a , l ( d i r ) , y a d d b a , i m m s u b b a , i m m movmb abs/dir,x m o v m a b s / d i r , x ldad e,l(dir),y b r a r e l movmb dir/imm movmb abs/imm stab a,l(dir),y sta a,l(dir),y stad e,l(dir),y l d a b a , ( d i r ) , y l d a a , ( d i r ) , y l d a b a , i m m c m p b a , i m m m o v m b d i r / d i r movm dir/dir m o v m b a b s / d i r m o v m a b s / d i r ldad e,(dir),y orab a,imm andb a,imm eorb a,imm stab a,(dir),y sta a,(dir),y s t a d e , ( d i r ) , y bs r rel t a b l e 1 h e x a d e c i m a l n o t a t i o n p l d n / r t s d n stk / r t l d n ldd n / p h l d n / p h d n n o t e : t a b l e s 1 t h r o u g h 1 4 s p e c i f i e s t h e c o n t e n t s o f t h e i n s t r u c t i o n c o d e t a b l e 1 t h r o u g h 1 4 . a b o u t t h e s e c o n d w o r d s c o d e s , r e f e r t o t h e i n s t r u c t i o n c o d e t a b l e 1 t h r o u g h 1 4 .
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-47 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 101000 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1 1010 1011 1100 1101 1110 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1101 1 1 1 0 1 1 1 1 dxbne imm,rel a d d x i m m addy imm s u b x i m m s u b y i m m dybne imm,rel bss a,b,rel bsc a,b,rel d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 1 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 0 1 1 6 ) h e x a d e c i m a l n o t a t i o n 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0 0 0 10 0 1 000110 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 011011 1 1 01 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 l d a b a , ( d i r ) l d a a , ( d i r ) a d d a , ( d i r ) s u b a , ( d i r ) c m p a , ( d i r ) o r a a , ( d i r ) a n d a , ( d i r ) e o r a , ( d i r ) l d a d e , ( d i r ) a d d d e , ( d i r ) s u b d e , ( d i r ) c m p d e , ( d i r ) s t a b a , ( d i r ) s t a a , ( d i r ) stad e,(dir) l d a b a , ( d i r , x ) l d a a , ( d i r , x ) a d d a , ( d i r , x ) s u b a , ( d i r , x ) c m p a , ( d i r , x ) o r a a , ( d i r , x ) a n d a , ( d i r , x ) e o r a , ( d i r , x ) l d a d e , ( d i r , x ) addd e,(dir,x) s u b d e , ( d i r , x ) c m p d e , ( d i r , x ) s t a b a , ( d i r , x ) s t a a , ( d i r , x ) s t a d e , ( d i r , x ) l d a b a , l ( d i r ) l d a a , l ( d i r ) a d d a , l ( d i r ) s u b a , l ( d i r ) c m p a , l ( d i r ) o r a a , l ( d i r ) a n d a , l ( d i r ) e o r a , l ( d i r ) l d a d e , l ( d i r ) a d d d e , l ( d i r ) s u b d e , l ( d i r ) c m p d e , l ( d i r ) s t a b a , l ( d i r ) s t a a , l ( d i r ) stad e,l(dir) l d a b a , s r l d a a , s r a d d a , s r s u b a , s r c m p a , s r o r a a , s r a n d a , s r e o r a , s r l d a d e , s r a d d d e , s r s u b d e , s r c m p d e , s r s t a b a , s r s t a a , s r s t a d e , s r l d a b a , ( s r ) , y l d a a , ( s r ) , y a d d a , ( s r ) , y s u b a , ( s r ) , y c m p a , ( s r ) , y ora a,(sr),y a n d a , ( s r ) , y e o r a , ( s r ) , y l d a d e , ( s r ) , y a d d d e , ( s r ) , y s u b d e , ( s r ) , y c m p d e , ( s r ) , y s t a b a , ( s r ) , y s t a a , ( s r ) , y s t a d e , ( s r ) , y l d a b a , a b s , y l d a a , a b s , y a d d a , a b s , y s u b a , a b s , y c m p a , a b s , y o r a a , a b s , y a n d a , a b s , y e o r a , a b s , y l d a d e , a b s , y addd e,abs,y s u b d e , a b s , y c m p d e , a b s , y s t a b a , a b s , y s t a a , a b s , y s t a d e , a b s , y add a,(dir),y s u b a , ( d i r ) , y c m p a , ( d i r ) , y ora a,(dir),y and a,(dir),y e o r a , ( d i r ) , y addd e,(dir),y subd e,(dir),y c m p d e , ( d i r ) , y a d d a , l ( d i r ) , y s u b a , l ( d i r ) , y cmp a,l(dir),y o r a a , l ( d i r ) , y a n d a , l ( d i r ) , y eor a,l(dir),y addd e,l(dir),y s u b d e , l ( d i r ) , y c m p d e , l ( d i r ) , y a d d a , a b l s u b a , a b l c m p a , a b l o r a a , a b l a n d a , a b l e o r a , a b l a d d d e , a b l s u b d e , a b l c m p d e , a b l add a,abl,x s u b a , a b l , x c m p a , a b l , x ora a,abl,x and a,abl,x e o r a , a b l , x a d d d e , a b l , x s u b d e , a b l , x c m p d e , a b l , x d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 2 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 1 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-48 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0 0 0 10 0 1 00 0 1 101000 1 0 1 0110 0111 1000 1 0 0 11 0 1 010111 1 0 01 1 0 111101 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1011 1 1 0 0 1 1 0 1 1 1 1 0 1111 a d c a , ( d i r ) a d c d e , ( d i r ) sbc a,(dir) s b c d e , ( d i r ) m p y ( d i r ) mpys (dir) d i v ( d i r ) divs (dir) a d c a , ( d i r , x ) adcd e,(dir,x) sbc a,(dir,x) s b c d e , ( d i r , x ) m p y ( d i r , x ) m p y s ( d i r , x ) d i v ( d i r , x ) divs (dir,x) a d c a , l ( d i r ) a d c d e , l ( d i r ) sbc a,l(dir) sbcd e,l(dir) m p y l ( d i r ) m p y s l ( d i r ) d i v l ( d i r ) divs l(dir) a d c a , s r adcd e,sr sbc a,sr s b c d e , s r mpy sr m p y s s r d i v s r divs sr a d c a , ( s r ) , y a d c d e , ( s r ) , y sbc a,(sr),y sbcd e,(sr),y mpy (sr),y mpys (sr),y div (sr),y divs (sr),y adc a,(dir),y adcd e,(dir),y sbc a,(dir),y s b c d e , ( d i r ) , y m p y ( d i r ) , y m p y s ( d i r ) , y div (dir),y divs (dir),y a d c a , l ( d i r ) , y a d c d e , l ( d i r ) , y sbc a,l(dir),y s b c d e , l ( d i r ) , y mpy l(dir),y m p y s l ( d i r ) , y d i v l ( d i r ) , y divs l(dir),y a d c a , d i r a d c d e , d i r sbc a,dir s b c d e , d i r m p y d i r mpys dir div dir divs dir a d c a , d i r , x adcd e,dir,x sbc a,dir,x s b c d e , d i r , x m p y d i r , x mpys dir,x div dir,x divs dir,x a d c a , a b s , y a d c d e , a b s , y sbc a,abs,y sbcd e,abs,y mpy abs,y mpys abs,y div abs,y divs abs,y a d c a , a b s adcd e,abs sbc a,abs s b c d e , a b s m p y a b s m p y s a b s d i v a b s divs abs adc a,abs,x a d c d e , a b s , x sbc a,abs,x s b c d e , a b s , x mpy abs,x m p y s a b s , x d i v a b s , x divs abs,x adc a,abl a d c d e , a b l sbc a,abl sbcd e,abl mpy abl m p y s a b l d i v a b l divs abl a d c a , a b l , x a d c d e , a b l , x sbc a,abl,x s b c d e , a b l , x m p y a b l , x m p y s a b l , x d i v a b l , x divs abl,x a s l d i r r o l d i r l s r d i r r o r d i r a s r d i r asl dir,x rol dir,x lsr dir,x r o r d i r , x asr dir,x a s l a b s rol abs l s r a b s ror abs a s r a b s a s l a b s , x r o l a b s , x l s r a b s , x r o r a b s , x a s r a b s , x d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 3 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 2 1 1 6 ) hexadecimal notation 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 1 0110 0111 1 0 0 01 0 0 11 0 1 01 0 1 111001 1 0 111101111 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 w i t i m p s t p i m p pht stk p l t s t k p h g s t k n e g d e a b s d e e x t z d e e x t s d e t a d , 0 i m p t a d , 1 i m p t a d , 2 i m p t a d , 3 i m p tda,0 imp t d a , 1 i m p t d a , 2 i m p tda,3 imp t a s i m p t s a i m p t x y i m p t y x i m p txs imp a d c a , i m m sbc a,imm m o v m d i r , x / i m m m o v m a b s , x / i m m rla a mpy imm mpys imm div imm a d d s i m m a d c b a , i m m m v p b l k m o v m b d i r , x / i m m ldt imm r m p a m u l t i p l i e d a c c u m u l a t i o n tsx imp d i v s i m m s u b s i m m s b c b a , i m m m v n b l k movmb abs,x/imm p e i s t k a d c d e , i m m p e a s t k jmp (abs) sbcd e,imm p e r s t k jmpl l(abs) t d s i m p t s d i m p d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 4 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 3 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-49 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0 0111 1000 1001 1010 1 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1011 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 b b s d i r , b , r e l b b c d i r , b , r e l cbeq dir/imm,rel ldy dir,x i n c d i r , x dec dir,x c p x a b s b b s a b s , b , r e l bbc abs,b,rel l d y a b s , x i n c a b s , x dec abs,x ldx dir,y ldx abs,y stx dir,y sty dir,x c p y a b s cbne dir/imm,rel d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 5 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 4 1 1 6 ) h e x a d e c i m a l n o t a t i o n 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 101000 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1 1010 1011 1100 1101 1110 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 a d d m d d i r / i m m submd dir/imm c m p m d d i r / i m m oramd dir/imm a n d m d d i r / i m m e o r m d d i r / i m m a d d m b d i r / i m m s u b m b d i r / i m m c m p m b d i r / i m m o r a m b d i r / i m m andmb dir/imm e o r m b d i r / i m m a d d m d i r / i m m subm dir/imm c m p m d i r / i m m o r a m d i r / i m m a n d m d i r / i m m e o r m d i r / i m m addmd abs/imm s u b m d a b s / i m m cmpmd abs/imm o r a m d a b s / i m m andmd abs/imm e o r m d a b s / i m m a d d m b a b s / i m m submb abs/imm cmpmb abs/imm oramb abs/imm andmb abs/imm e o r m b a b s / i m m a d d m a b s / i m m s u b m a b s / i m m c m p m a b s / i m m oram abs/imm andm abs/imm e o r m a b s / i m m d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 6 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 5 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-50 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 0 0011 0100 0 1 0 10 1 1 0011110001 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01111 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1010 1011 1 1 0 0 1 1 0 1 1 1 1 0 1111 m o v r b d i r / a b s movr dir/abs movrb abs/abs movr abs/abs m o v r b d i r / i m m movr dir/imm m o v r b a b s / i m m movr abs/imm m o v r b d i r / d i r movr dir/dir m o v r b a b s / d i r movr abs/dir d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 7 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 6 1 1 6 ) h e x a d e c i m a l n o t a t i o n 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 101000 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1 1010 1011 1100 1101 1110 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bss dir,b,rel bsc dir,b,rel b s c a b s , b , r e l m o v r b d i r / a b s , x b s s a b s , b , r e l m o v r d i r / a b s , x m o v r b a b s / d i r , x m o v r a b s / d i r , x d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 8 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 7 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-51 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 1 0110 0111 1000 1 0 0 11 0 1 010111 1 0 01 1 0 111101 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1010 1 0 1 1 1 1 0 0 1 1 0 1 1110 1 1 1 1 a s l b n e g b lda b,imm l d a b b , a b s , x rol b abs b e x t z b a d d b , i m m e x t s b sub b,imm l s r b c l r b b c m p b , i m m r o r b c l r b o r a b , i m m and b,imm a s r b eor b,imm inc b p h b s t k d e c b p l b s t k txb imp c b n e b b / i m m , r e l t y b i m p cbeq b/imm,rel l d a b , a b s , x a d d b , a b s , x s u b b , a b s , x c m p b , a b s , x o r a b , a b s , x a n d b , a b s , x e o r b , a b s , x stab b,abs,x sta b,abs,x tbx imp t b y i m p c b n e b / i m m , r e l l d a b b , a b s lda b,abs a d d b , a b s sub b,abs c m p b , a b s ora b,abs a n d b , a b s e o r b , a b s s t a b b , a b s s t a b , a b s l d a b b , a b l , x l d a b , a b l , x s t a b b , a b l , x s t a b , a b l , x ldab b,abl l d a b , a b l stab b,abl sta b,abl l d a b b , d i r , x lda b,dir,x a d d b , d i r , x sub b,dir,x cmp b,dir,x ora b,dir,x a n d b , d i r , x eor b,dir,x s t a b b , d i r , x s t a b , d i r , x l d a b b , d i r lda b,dir a d d b , d i r s u b b , d i r c m p b , d i r o r a b , d i r a n d b , d i r e o r b , d i r s t a b b , d i r s t a b , d i r l d a b b , l ( d i r ) , y l d a b , l ( d i r ) , y addb b,imm s u b b b , i m m s t a b b , l ( d i r ) , y s t a b , l ( d i r ) , y l d a b b , ( d i r ) , y l d a b , ( d i r ) , y l d a b b , i m m cmpb b,imm orab b,imm andb b,imm eorb b,imm stab b,(dir),y sta b,(dir),y cbeqb b/imm,rel d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 9 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 8 1 1 6 ) h e x a d e c i m a l n o t a t i o n 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0 0 1 0 0011 0100 0101 0 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 l d a b b , ( d i r ) l d a b , ( d i r ) a d d b , ( d i r ) s u b b , ( d i r ) c m p b , ( d i r ) o r a b , ( d i r ) a n d b , ( d i r ) e o r b , ( d i r ) s t a b b , ( d i r ) s t a b , ( d i r ) l d a b b , ( d i r , x ) l d a b , ( d i r , x ) a d d b , ( d i r , x ) s u b b , ( d i r , x ) c m p b , ( d i r , x ) o r a b , ( d i r , x ) a n d b , ( d i r , x ) e o r b , ( d i r , x ) s t a b b , ( d i r , x ) s t a b , ( d i r , x ) ldab b,l(dir) lda b,l(dir) add b,l(dir) s u b b , l ( d i r ) c m p b , l ( d i r ) o r a b , l ( d i r ) and b,l(dir) e o r b , l ( d i r ) s t a b b , l ( d i r ) s t a b , l ( d i r ) l d a b b , s r l d a b , s r a d d b , s r s u b b , s r c m p b , s r o r a b , s r a n d b , s r e o r b , s r s t a b b , s r s t a b , s r l d a b b , ( s r ) , y lda b,(sr),y a d d b , ( s r ) , y s u b b , ( s r ) , y cmp b,(sr),y ora b,(sr),y a n d b , ( s r ) , y eor b,(sr),y stab b,(sr),y sta b,(sr),y ldab b,abs,y lda b,abs,y add b,abs,y sub b,abs,y cmp b,abs,y o r a b , a b s , y and b,abs,y eor b,abs,y stab b,abs,y sta b,abs,y a d d b , ( d i r ) , y sub b,(dir),y cmp b,(dir),y o r a b , ( d i r ) , y a n d b , ( d i r ) , y eor b,(dir),y add b,l(dir),y sub b,l(dir),y c m p b , l ( d i r ) , y ora b,l(dir),y and b,l(dir),y e o r b , l ( d i r ) , y a d d b , a b l s u b b , a b l c m p b , a b l ora b,abl a n d b , a b l e o r b , a b l a d d b , a b l , x s u b b , a b l , x cmp b,abl,x o r a b , a b l , x a n d b , a b l , x eor b,abl,x d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 1 0 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s 9 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-52 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 1 0110 0111 1000 1 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01111 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1101 1 1 1 0 1111 a d c b , ( d i r ) sbc b,(dir) a d c b , ( d i r , x ) sbc b,(dir,x) a d c b , l ( d i r ) sbc b,l(dir) a d c b , s r sbc b,sr adc b,(sr),y sbc b,(sr),y a d c b , ( d i r ) , y sbc b,(dir),y adc b,l(dir),y sbc b,l(dir),y a d c b , d i r sbc b,dir a d c b , d i r , x sbc b,dir,x adc b,abs,y sbc b,abs,y adc b,abs sbc b,abs a d c b , a b s , x sbc b,abs,x a d c b , a b l sbc b,abl a d c b , a b l , x sbc b,abl,x d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 1 1 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s a 1 1 6 ) h e x a d e c i m a l n o t a t i o n 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 000110 1 0 00 1 0 1 0110 0111 1000 1001 1 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 t b d , 0 i m p t b d , 1 i m p t b d , 2 i m p t b d , 3 i m p t d b , 0 i m p t d b , 1 i m p t d b , 2 i m p t d b , 3 i m p t b s i m p t s b i m p adc b,imm sbc b,imm a d c b b , i m m s b c b b , i m m d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 1 2 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s b 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 5. hexadecimal instruction code table 7906 group user s manual rev.2.0 20-53 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 101100 1 1 11 0 0 01 0 0 110101 0 1 111001 1 0 111101 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1011 1 1 0 0 1 1 0 1 1110 1111 debne dir/imm,rel a s r , # n a asl,#n a r o l , # n a lsr,#n a r o r , # n a d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 1 3 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s c 1 1 6 ) h e x a d e c i m a l n o t a t i o n 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 1 0110 0111 1 0 0 010011 0 1 01 0 1 11 1 0 01 1 0 111101 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 d e b n e a b s / i m m , r e l a s r d , # n e a s l d , # n e r o l d , # n e lsrd,#n e r o r d , # n e d 3 d 0 d 7 d 4 i n s t r u c t i o n c o d e t a b l e 1 4 ( t h e f i r s t w o r d s c o d e o f e a c h i n s t r u c t i o n i s d 1 1 6 ) h e x a d e c i m a l n o t a t i o n
appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-54 appendix 6. machine instructions note: for an instruction of which ?peration length (bit)?= 16/8 is executed in the bit length described below. ?16-bit length when m = 0 or x = 0. ?8-bit length when m = 1 or x = 1. for an instruction of which ?peration length (bit)?= 8 or 32 is executed in 8-bit or 32-bit length regardless of the contents of flags m and x.
appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-55 imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y l(dir) l(dir), y abs abs, x abs, y abl abl, x (abs) l(abs) (abs, x) stk rel dir, b, r abs, b, r sr (sr), y blk multiplied accumulation op n # c z i d x m v n ipl + ? ? | | ? ? acc acc h acc l a a h a l b b h b l e e h e l x x h x l y y h y l s rel pc pc h pc l pg dt dpr0 dpr0 h dpr0 l dprn dprn h dprn l ps ps h ps l ps l (bit n) m m(s) m(bit n) mn imm immn imm h imm l ad h ad m ad l ear ear h ear l imm imm n dd i i 1 , i 2 source dest symbol description description implied addressing mode immediate addressing mode accumulator addressing mode direct addressing mode direct indexed x addressing mode direct indexed y addressing mode direct indirect addressing mode direct indexed x indirect addressing mode direct indirect indexed y addressing mode direct indirect long addressing mode direct indirect long indexed y addressing mode absolute addressing mode absolute indexed x addressing mode absolute indexed y addressing mode absolute long addressing mode absolute long indexed x addressing mode absolute indirect addressing mode absolute indirect long addressing mode absolute indexed x indirect addressing mode stack addressing mode relative addressing mode direct bit relative addressing mode absolute bit relative addressing mode stack pointer relative addressing mode stack pointer relative indirect indexed y addressing mode block transfer addressing mode multiplied accumulation addressing mode instruction code (op code) number of cycles number of bytes carry flag zero flag interrupt disable flag decimal operation mode flag index register length selection flag data length selection flag overflow flag negative flag processor interrupt priority level addition subtraction multiplication division logical and logical or logical exclusive or absolute value negation movement to the arrow direction movement to the arrow direction exchange accumulator accumulator? high-order 8 bits accumulator? low-order 8 bits accumulator a accumulator a? high-order 8 bits accumulator a? low-order 8 bits accumulator b accumulator b? high-order 8 bits accumulator b? low-order 8 bits accumulator e accumulator e? high-order 16 bits (accumulator b) accumulator e? low-order 16 bits (accumulator a) index register x index register x? high-order 8 bits index register x? low-order 8 bits index register y index register y? high-order 8 bits index register y? low-order 8 bits stack pointer relative address program counter program counter? high-order 8 bits program counter? low-order 8 bits program bank register data back register direct page register 0 direct page register 0? high-order 8 bits direct page register 0? low-order 8 bits direct page register n direct page register n? high-order 8 bits direct page register n? low-order 8 bits processor status register processor status register? high-order 8 bits processor status register? low-order 8 bits nth bit in processor status register contents of memory contents of memory at address indicated by stack pointer nth bit of memory n-bit memory? address or contents immediate value (8 bits or 16 bits) n-bit immediate value 16-bit immediate value? high-order 8 bits 16-bit immediate value? low-order 8 bits value of 24-bit address? high-order 8 bits (a 23 ? 16 ) value of 24-bit address? middle-order 8 bits (a 15 ? 8 ) value of 24-bit address? low-order 8 bits (a 7 ? 0 ) effective address (16 bits) effective address? high-order 8 bits effective address? low-order 8 bits 8-bit immediate value n-bit immediate value displacement for dpr (8 bits or 16 bits) number of transfer bytes, rotation or repeated operations number of registers pushed or pulled operand to specify transfer source operand to specify transfer destination symbol
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-56 21 12 3 99 11 9 3 29 91 9 3 29 21 10 3 89 a1 12 3 89 7900 series machine instructions acc | acc | abs (note 1) e1 3 1 81 4 2 e1 31 4 6 1c 21 7 3 9a 21 8 3 9b 21 9 3 90 21 10 3 91 21 10 3 98 21 11 3 92 11 7 3 21 11 6 3 20 2b 4 2 26 1 2 2a 3 2 11 7 3 28 11 8 3 22 91 7 3 21 91 6 3 20 81 5 3 2b 81 2 3 26 81 4 3 2a 91 7 3 28 91 8 3 22 29 1 2 81 2 3 29 16/8 32 16/8 8 16/8 21 8 3 81 21 7 3 80 21 6 3 8b 31 3 3 87 21 5 3 8a 21 8 3 88 21 9 3 82 a1 10 3 81 a1 9 3 80 a1 8 3 8b b1 3 3 87 a1 7 3 8a a1 10 3 88 a1 11 3 82 acc acc + m + c adc (notes 1 and 2) e | e | absd acc l acc l + imm8 + c adcb (note 1) 31 5 2 90 31 3 3 1a b1 3 3 1a 32 8 acc l acc l + imm8 e e + m32 + c add (notes 1 and 2) addb (note 1) acc acc + m adcd 11 12 3 99 s s + imm8 adds m8 m8 + imm8 addmb m m + imm e e + m32 addd addm (note 3) m32 m32 + imm32 addmd 11 10 3 91 11 9 3 90 9b 7 2 2d 3 5 51 7 4 03 11 10 3 98 11 11 3 92 51 7 4 02 51 10 7 83 31 2 3 0a 9a 6 2 y y + imm (imm = 0 to 31) addx addy (note 4) x x + imm (imm = 0 to 31) 01 2 2 01 2 2 20 + imm 32 16/8 8 32 16 16/8 16/8
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-57 21 7 4 9e 21 8 4 96 21 8 5 9c 21 9 5 9d 21 8 3 93 21 11 3 94 2e 3 3 2f 4 3 11 5 4 26 11 6 5 2d 11 5 5 2c 11 5 3 93 11 8 3 24 81 4 4 2e 81 5 4 2f 91 5 4 26 91 6 5 2d 91 5 5 2c 91 5 3 23 91 8 3 24 0v z0 nv zc nv zc nv zc 21 8 4 9f nv zc 21 5 4 8e 21 6 4 8f 21 6 4 86 21 7 5 8d 21 6 5 8c 21 6 3 83 21 9 3 84 a1 7 4 8e a1 8 4 8f a1 8 4 86 a1 9 5 8d a1 8 5 8c a1 8 3 83 a1 11 3 84 0v z0 nv zc nv zc 9e 6 3 9f 7 3 11 8 4 96 11 9 5 9d 11 8 5 9c 11 8 3 93 11 11 3 94 nv zc 51 7 5 07 nv zc 51 7 5 06 51 10 8 87 nv zc nv zc nv zc nv zc
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-58 b 15 ?b 0 c b 7 ?b 0 c b 15 ?b 0 c b 7 ?b 0 c c b 15 ?b 0 0 c b 7 ?b 0 0 c b 15 ?b 0 0 c b 7 ?b 0 0 arithmetic shift to the right by n bits (n = 0 to 15) m = 0 m = 1 arithmetic shift to the right by 1 bit m = 0 acc or m16 m = 1 acc l or m8 arithmetic shift to the left by n bits (n = 0 to 31) e arithmetic shift to the left by n bits (n = 0 to 15) m = 0 a m = 1 a l arithmetic shift to the left by 1 bit m = 0 acc or m16 m = 1 acc l or m8 11 9 3 69 91 9 3 69 asl (note 1) m32 m32 imm32 asl #n (note 4) andmd m m imm andm (note 3) acc l acc l imm8 andb (note 1) m8 m8 imm8 andmb 81 4 3 6a acc acc m 11 7 3 61 11 6 3 60 66 1 2 11 7 3 68 11 8 3 62 91 7 3 61 91 6 3 60 81 5 3 6b 81 2 3 66 91 7 3 68 and (notes 1 and 2) 91 8 3 62 6a 3 2 6b 4 2 23 1 2 81 2 3 23 51 7 4 63 51 7 4 62 51 10 7 e3 03 1 1 81 2 2 03 21 7 3 0a 21 8 3 0b c1 6 2 40 + + imm imm asld #n (note 4) 64 1 121 7 3 4a 21 8 3 4b 81 2 2 64 asr (note 1) d1 8 2 40 + + imm imm c b 31 ?b 0 0 asr #n (note 4) c1 6 2 80 + + imm imm 16/8 8 16/8 8 32 16/8 16/8 32 16/8 16/8 a a l
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-59 nz 6e 3 3 6f 4 3 11 5 4 66 11 6 5 6d 11 5 5 6c 11 5 3 63 11 8 3 64 81 4 4 6e 81 5 4 6f 91 5 4 66 91 6 5 6d 91 5 5 6c 91 5 3 63 91 8 3 64 21 7 4 0e 21 8 4 0f n zc nz nz nz n zc nz 51 7 5 67 51 7 5 66 51 10 8 e7 nzc 21 7 4 4e 21 8 4 4f n zc nzc
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-60 arithmetic shift to the right by n bits (n = 0 to 31) if c = 0 then pc pc + 2 + rel (?28 to +127) bcc if m(bit n) = 0 then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) bbc (note 3) asrd #n (note 4) if m8(bit n) = 0 then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) bbcb if m(bit n) = 1 then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) bbs (note 3) if m8(bit n) = 1 then pc pc+cnt+rel (?28 to +127) (cnt: number of bytes of instruction) bbsb if c = 1 then pc pc + 2 + rel (?28 to +127) bcs if z = 1 then pc pc + 2 + rel (?28 to +127) beq d1 8 2 80 + + imm imm bge bgt bgtu ble bleu if z = 0 and n ? v = 0 then pc pc + 2 + rel (?28 to +127) if c = 1 and z = 0 then pc pc + 2 + rel (?28 to +127) blt 32 16/8 8 16/8 8 if n ? v = 0 then pc pc + 2 + rel (?28 to +127) if z = 1 or n ? v = 1 then pc pc + 2 + rel (?28 to +127) if c = 0 or z = 1 then pc pc + 2 + rel(?28 to +127) if n ? v = 1 then pc pc + 2 + rel (?28 to +127) e b 31 ?b 0 c
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-61 41 9 6 5e 41 9 5 5a 57 8 5 52 8 4 41 9 6 4e 41 9 5 4a 47 8 5 42 8 4 90 6 2 b0 6 2 f0 6 2 nzc c0 6 2 80 6 2 40 6 2 a0 6 2 60 6 2 e0 6 2
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-62 bmi bne bpl pc pc + cn t + rel (bra:?28 to +127, bral: ?2768 to +32767) (cnt: number of bytes of instruction) pg pg + 1 (when carry occurs) pg pg ?1 (when borrow occurs) bra/bral (note 5) pc pc + 2 m(s) pg s s ?1 m(s) pc h s s ?1 m(s) pc l s s ?1 m(s) ps h s s ?1 m(s) ps l s s ?1 i 1 pc l ad l pc h ad m pg 00 16 or ff 16 brk (note 6) 00 15 2 74 bvc bvs bsr bss (note 7) bsc (note 7) 01 7 3 a0 + n 71 11 4 a0 + n 01 7 3 80 + n 71 11 4 80 + n (s) pc + 2 pc pc + 2 + rel (?024 to +1023) 16/8 16/8 if n = 1 then pc pc + 2 + rel (?28 to +127) if z = 0 then pc pc + 2 + rel (?28 to +127) if n = 0 then pc pc + 2 + rel (?28 to +127) if a(bit n) or m(bit n) = 0 (n = 0 to 15), then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) if a(bit n) or m(bit n) = 1 (n = 0 to 15), then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) if v = 0 then pc pc + 2 + rel (?28 to +127) if v = 1 then pc pc + 2 + rel (?28 to +127)
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-63 d0 6 2 30 6 2 10 6 2 a7 5 3 20 5 2 1 50 6 2 70 6 2 71 10 5 e + n 71 10 5 c0 + n f8 7 2 | ff
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-64 c 0 clc i 0 cli m 0 clm 45 3 1 14 1 1 15 3 1 cbne (notes 1 and 3) cbneb (note 1) b6 6 3 41 9 5 7a 81 7 4 b6 b2 6 3 72 8 4 81 7 4 b2 ps l (bit n) 0 (n = 0 to 7. multiple bits can be specified.) clp 98 4 2 acc 0 clr (note 1) acc l 00 16 clrb (note 1) 54 1 1 81 2 2 54 44 1 1 81 2 2 44 x 0 clrx y 0 clry e4 1 1 f4 1 1 m 0 clrm m8 00 16 clrmb d2 5 2 c2 5 2 a6 6 3 41 9 5 6a 81 7 4 a6 cbeq (notes 1 and 3) cbeqb (note 1) a2 6 3 62 8 4 81 7 4 a2 16/8 8 16/8 8 16/8 8 16/8 8 16/8 16/8 if acc = imm or m = imm then pc pc + cnt + rel(?28 to +127) (cnt: number of bytes of instruction) if acc l = imm8 or m8 = imm8 then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) if acc imm or m imm then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) if acc l imm8 or m8 imm8 then pc pc+cnt+rel(?28 to +127) (cnt: number of bytes of instruction)
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-65 0 0 0 nv z c nv z c 0 1 01 0 1 0 1 d7 5 3 c7 5 3 nv z c nv z c specified flag becomes ?.
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-66 11 9 3 49 91 9 3 49 11 12 3 b9 v 0 clv 65 1 1 acc ?m cmp (notes 1 and 2) 46 1 2 4a 3 2 81 4 3 4a 4b 4 2 81 5 3 4b 11 6 3 40 91 6 3 40 11 7 3 41 91 7 3 41 11 7 3 48 91 7 3 48 11 8 3 42 91 8 3 42 81 2 3 46 acc l ?imm8 cmpb (note 1) e ?m32 cmpd m ?imm cmpm (note 3) m8 ?imm8 cmpmb m32 ?imm32 cmpmd 38 1 2 81 2 3 38 3c 3 5 ba 6 2 bb 7 2 11 9 3 b0 11 10 3 b1 11 10 3 b8 11 11 3 b2 51 5 4 23 51 5 4 22 51 7 7 a3 x ?m cpx (note 8) e6 1 2 22 3 2 y ?m cpy (note 8) f6 1 2 32 3 2 21 21 3 e9 acc acc ?1 or m m ?1 dec (note 1) b3 1 1 41 8 3 9b 81 2 2 b3 x x ?1 dex e3 1 1 92 6 2 m m ?imm(imm = 0 to 31) if m 0, then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) debne (note 4) f3 1 1 y y ?1 dey 31 15 3 e7 21 16 3 ea 21 17 3 eb 21 18 3 e0 21 19 3 e1 21 19 3 e8 21 20 3 e2 a (quotient) (b, a) ?m b (remainder) div (notes 2, 9, and 10) c1 12 4 a0 + imm 16/8 8 32 16/8 8 32 16/8 16/8 16/8 16/8 16/8 16/8 16/8
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-67 11 5 4 46 0 nv z c 11 6 5 4d 11 8 3 44 91 8 3 44 91 5 3 43 91 5 4 46 91 5 5 4c 81 5 4 4f 4f 4 3 4e 3 3 81 4 4 4e 11 5 5 4c 91 6 5 4d 11 5 3 43 nv z c nv z c nv z c nv z c nv z c 11 8 4 b6 11 9 5 bd 11 11 3 b4 bf 7 3 be 6 3 11 8 5 bc 11 8 3 b3 51 5 5 27 51 5 5 26 51 7 8 a7 41 4 4 2e nv z c 41 4 4 3e nv z c nz 97 6 341 8 4 9f n z nz nv i z c 21 17 4 ef 21 17 4 e6 21 18 5 ed 21 17 3 e3 21 20 3 e4 21 16 4 ee 21 17 5 ec d1 11 5 e0 + imm
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-68 21 28 3 f9 a (quotient) (b, a) ?m b (remainder) (signed) divs (notes 2, 9, and 10) 31 22 3 f7 21 23 3 fa 21 24 3 fb 21 25 3 f0 21 26 3 f1 21 26 3 f8 21 27 3 f2 x x ?imm (imm = 0 to 31) if x 0, then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) dxbne (note 4) y y ?imm (imm = 0 to 31) if y 0, then pc pc + cnt + rel (?28 to +127) (cnt: number of bytes of instruction) dybne (note 4) 01 7 3 c0 + imm 01 7 3 e0 + imm 11 9 3 79 91 9 3 79 acc l acc l ? immb eorb (note 1) m m ? imm eorm (note 3) m8 m8 ? imm8 eormb m32 m32 ? imm32 eormd 33 1 2 81 2 3 33 51 7 4 73 51 7 4 72 51 10 7 f3 91 8 3 72 11 8 3 72 acc acc ? m eor (notes 1 and 2) 76 1 2 7a 3 2 7b 4 2 11 6 3 70 11 7 3 71 11 7 3 78 81 4 3 7a 81 5 3 7b 91 6 3 70 91 7 3 71 91 7 3 78 81 2 3 76 extzd extz (note 1) 81 2 2 34 34 1 1 00000000 b 15 b 8 b 7 b 0 acc acc l (extension sign) (bit 7 of acc l = 0) exts (note 1) (bit 7 of acc l = 1) 35 1 1 00000000 0 b 15 b 7 b 0 11111111 1 b 15 b 7 b 0 81 2 2 35 extsd 31 5 2 b0 31 3 2 a0 e e l (= a) (extension sign) (bit 15 of a = 0) (bit 15 of a = 1) 0000 16 0 b 15 b 0 b 15 b 0 ffff 16 1 b 15 b 0 b 15 b 0 0000 16 b 15 b 0 b 15 b 0 e h (b) e l (a) e h (b) e l (a) e h (b) e l (a) 16/8 16/8 16/8 16/8 8 16/8 8 32 16 32 16 32 acc acc l (extension zero) e e l (= a) (extension zero) acc h acc l acc h acc l acc h acc l
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-69 nv i z c 21 24 4 f6 21 25 5 fd 21 24 3 f3 21 27 3 f4 21 23 4 fe 21 24 5 fc 21 24 4 ff nz nz n z n z 51 7 5 77 51 7 5 76 51 10 8 f7 n z 7e 3 3 7f 4 3 11 5 4 76 11 5 5 7c 11 6 5 7d 11 5 3 73 11 8 3 74 81 4 4 7e 81 5 4 7f 91 5 4 76 91 5 5 7c 91 6 5 7d 91 5 3 73 91 8 3 74 0 z nz n z 0 z
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-70 inc (note 1) acc acc + 1 or m m + 1 a3 1 1 81 2 2 a3 82 6 2 41 8 3 8b c3 1 1 d3 1 1 inx x x + 1 iny y y + 1 jmp/jmpl when abs specified pc l ad l pc h ad m when abl specified pc l ad l pc h ad m pg ad h when (abs) specified pc l (ad m, ad l ) pc h (ad m, ad l + 1) when l(abs) specified pc l (ad m, ad l ) pc h (ad m, ad l + 1) pg (ad m, ad l + 2) when (abs,x) specified pc l (ad m, ad l + x) pc h (ad m, ad l + x + 1) when abs specified pc pc + 3 m(s) pc h s s? m(s) pc l s s? pc l ad l pc h ad m when abl specified pc pc + 4 m(s) pg s s ?1 m(s) pc h s s ?1 m(s) pc l s s ?1 pc l ad l pc h ad m pg ad h when (abs,x) specified pc pc + 3 m(s) pc h s s ?1 m(s) pc l s s ?1 pc l (ad m , ad l + x) pc h (ad m , ad l + x + 1) jsr/jsrl 19 8 2 81 9 3 19 09 8 2 81 2 3 16 acc m lda (notes 1 and 2) 1a 3 2 81 4 3 1a 1b 4 2 81 5 3 1b 11 6 3 10 91 6 3 10 11 7 3 11 91 7 3 11 18 6 2 81 7 3 18 11 8 3 12 91 8 3 12 16 1 2 acc m8 (extension zero) ldab (note 1) 0a 3 2 0b 4 2 11 6 3 00 11 7 3 01 08 6 2 11 8 3 02 28 1 2 81 9 3 09 81 7 3 08 91 7 3 01 81 2 3 28 81 4 3 0a 81 5 3 0b 91 6 3 00 91 8 3 02 16/8 16/8 16/8 16/8 16
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-71 nz 41 8 4 8f nz nz 9c 4 3 ac 5 4 31 7 4 5c 31 9 4 5d bc 7 3 87 6 3 9d 6 3 ad 7 4 bd 8 3 1f 4 3 81 5 4 1f 1e 3 3 81 4 4 1e 1d 5 4 81 6 5 1d 1c 4 4 81 5 5 1c 11 5 4 16 91 5 4 16 11 8 3 14 91 8 3 14 11 5 3 13 91 5 3 13 nz 0f 4 3 0e 3 3 0d 5 4 0c 4 4 11 5 4 06 11 8 3 04 11 5 3 03 0 z 81 5 5 0c 81 5 4 0f 81 4 4 0e 81 6 5 0d 91 5 4 06 91 8 3 04 91 5 3 03
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-72 0 b 15 ?b 0 c 0 b 7 ?b 0 c 0 b 15 ?b 0 c 0 b 7 ?b 0 c logical shift to the right by n bits (n = 0 to 15) m = 0 a m = 1 a l logical shift to the right by 1 bit m = 0 acc or m16 m = 1 acc l or m8 89 11 2 dt imm8 ldt 31 4 3 4a x m ldx (note 8) c6 1 2 02 3 2 41 5 3 05 y m ldy (note 8) d6 1 2 12 3 2 41 5 3 1b e m32 ldad ldd n (notes 11 and 12) ldxb x imm8 (extension zero) 8a 6 2 8b 7 2 11 9 3 80 11 10 3 81 88 9 2 11 11 3 82 2c 3 5 b8 11 2 ?0 + + 2 i 2 i b8 13 4 ?0 27 1 2 dprn imm16 (n = 0 to 3. multiple dprs can be specified.) ldyb y imm8 (extension zero) 37 1 2 lsr (note 1) 21 8 3 2b 43 1 1 21 7 3 2a 81 2 2 43 lsr #n (note 4) lsrd #n (note 4) c1 6 2 + imm d1 8 2 + imm 32 16 8 16/8 16 16/8 16 16/8 16/8 32 logical shift to the right by n bits (n = 0 to 31) e 0 b 31 ?b 0 c
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-73 07 3 3 nz 41 5 4 06 17 3 3 nz 41 5 4 1f 8f 7 3 8e 6 3 8d 8 4 8c 7 4 11 8 4 86 11 11 3 84 11 8 3 83 nz 0 z 0z 21 7 4 2e 0zc 21 8 4 2f 0 zc 0zc
destination op n # imp imm a dir symbol op n # op n # op n # dir, x dir, y (dir) (dir, x) (dir), y l(dir) op n # op n # op n # op n # op n # op n # op n # function operation length (bit) l(dir), y appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-74 movr (notes 7 and 13) movrb (note 7) m = 0 m16(dest1) m16(source1) m16(dest n) m16(source n) m = 1 m8(dest1) m8(source1) m8(dest n) m8(source n) (n = 0 to 15) m8(dest1) m8(source1) m8(dest n) m8(source n) (n = to 15) m = 0 m16(dest) m16(source) m = 1 m8(dest) m8(source) movm (note 2) m8(dest) m8(source) movmb 86 5 3 31 7 4 47 58 6 3 5c 6 4 5d 7 4 a9 5 331 7 4 3a 48 6 3 4c 6 4 4d 7 4 61 3 2 10 + + + 5n 2n n 61 3 2 50 + + + 6n 2n n 61 3 2 90 + + + 6n 3n n 71 3 2 10 + + + 6n 3n n 61 3 2 00 + + + 5n 2n n 61 3 2 40 + + + 6n 2n n 61 3 2 80 + + + 6n 3n n 71 3 2 00 + + + 6n 3n n imm dir dir, x abs abs, x imm dir dir, x abs abs, x imm dir dir, x abs abs, x imm dir dir, x abs abs, x source 16/8 8 16/8 8 source source source
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa ipl n v m x d i z c destination processor status register 10 9 8 7 6 5 4 3 2 1 0 appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-75 96 4 431 6 5 57 78 5 4 79 6 4 7c 5 5 b9 4 431 6 5 3b 68 5 4 69 6 4 6c 5 5 61 3 2 30 + + + 4n 3n n 61 3 2 70 + + + 5n 3n n 71 3 2 70 + + + 6n 3n n 61 3 2 b0 + + + 5n 4n n 61 3 2 20 + + + 4n 3n n 61 3 2 60 + + + 5n 3n n 71 3 2 60 + + + 6n 3n n 61 3 2 a0 + + + 5n 4n n
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-76 21 14 3 c9 21 14 3 d9 mvp (note 16) (b, a) a ? m mpy (notes 2 and 14) 21 10 3 cb 31 8 3 c7 21 9 3 ca 21 11 3 c0 21 12 3 c1 21 12 3 c8 21 13 3 c2 (b, a) a ? m (signed) mpys (notes 2 and 14) 21 10 3 db 31 8 3 d7 21 9 3 da 21 11 3 d0 21 12 3 d1 21 12 3 d8 21 13 3 d2 mvn (note 15) pc pc + 1 when catty occurs in pc pg pg + 1 nop 74 1 1 acc ?cc neg (note 1) e ? negd 24 1 1 81 2 2 24 31 4 2 80 i: number of transfer bytes specified by accumulator a () () 11 9 3 59 91 9 3 59 m(s) imm h s s ?1 m(s) imm l s s ?1 pea m8 m8 imm8 oramb m32 m32 imm32 oramd 51 7 4 32 51 10 7 b3 m m imm oram (note 3) 56 1 2 acc acc m ora (notes 1 and 2) 81 2 3 56 5a 3 2 81 4 3 5a 5b 4 2 81 5 3 5b 11 6 3 50 91 6 3 50 11 7 3 51 91 7 3 51 11 7 3 58 91 7 3 58 11 8 3 52 91 8 3 52 acc l acc l imm8 orab (note 1) 63 1 2 81 2 3 63 51 7 4 33 m(s) m((dprn) + dd + 1) s s + 1 m(s) m((dprn)+dd) s s ?1 (n = 0 to 3) pei 16/8 16/8 16/8 16/8 16/8 32 16/8 8 16/8 8 32 16 16 i: number of transfer bytes specified by accumulator a m(y + k) m(x + k) k = 0 to i ?1 m(y?) m(x?) k = 0 to i?
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-77 n z0 21 9 4 ce 21 10 4 cf 21 10 4 c6 21 10 5 cc 21 11 5 cd 21 10 3 c3 21 13 3 c4 nz0 21 9 4 de 21 10 4 df 21 10 4 d6 21 10 5 dc 21 11 5 dd 21 10 3 d3 21 13 3 d4 31 5 4 2b + 5 i 31 9 4 2a + 5 i nv zc nv zc 31 5 4 4c n z n z 51 7 5 36 51 10 8 b7 n z 5e 3 3 81 4 4 5e 5f 4 3 81 5 4 5f 11 5 4 56 91 5 4 56 11 5 5 5c 91 5 5 5c 11 6 5 5d 91 6 5 5d 11 8 3 54 91 8 3 54 11 5 3 53 91 5 3 53 n z n z 51 7 5 37 31 7 3 4b
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-78 ear pc + imm16 m(s) ear h s s ?1 m(s) ear l s s ?1 per m = 0 m(s) a h s s ?1 m(s) a l s s ?1 m = 1 m(s) a l s s ?1 pha m = 0 m(s) b h s s ?1 m(s) b l s s ?1 m=1 m(s) b l s s ?1 phb m(s) dpr0 h s s ?1 m(s) dpr0 l s s ?1 phd phd n (note 11) m(s) pg s s ?1 phg phld n (note 11) m(s) dprn h s s ?1 m(s) dprn l s s ?1 (n = 0 to 3) when multiple dprs are specified, the above operations are repeated. m(s) dprn h s s ?1 m(s) dprn l s s ?1 dprn imm16 (n = 0 to 3) when multiple dprs are specified, the above operations are repeated. m(s) ps h s s ?1 m(s) ps l s s ?1 php m(s) dt s s ?1 pht 16 16/8 16/8 16 16 8 16 16 8
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-79 31 6 4 4d 85 4 1 81 5 2 85 83 4 1 b8 12 2 01 0f b8 11 2 01 + | i 0f 31 4 2 60 b8 14 4 01 | 0f b8 11 2 01 + + | 3 i 2 i 0f a5 4 1 31 4 2 40
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-80 x = 0 m(s) x h s s ?1 m(s) x l s s ?1 x = 1 m(s) x l s s ?1 phx x = 0 m(s) y h s s ?1 m(s) y l s s ?1 x = 1 m(s) y l s s ?1 phy m = 0 s s + 1 a l m(s) s s + 1 a h m(s) m = 1 s s + 1 a l m(s) pla m = 0 s s + 1 b l m(s) s s + 1 b h m(s) m = 1 s s + 1 b l m(s) plb s s + 1 dpr0 l m(s) s s + 1 dpr0 h m(s) pld pld n (notes 11 and 12) s s + 1 dprn l m(s) s s + 1 dprn h m(s) (n = 0 to 3) when multiple dprs are specified, the above operations are repeated. plp (note 22) s s + 1 ps l m(s) s s + 1 ps h m(s) plt s s + 1 dt m(s) 16/8 16/8 16/8 16/8 16 16 16 8
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-81 e5 4 1 c5 4 1 n z 95 4 1 81 5 2 95 n z 93 5 1 77 11 2 ?0 b5 5 1 31 6 2 50 n z value restored from stack 77 8 2 ?0 + 3 i
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-82 b 15 ?b 0 b 7 ?b 0 rotate to the left by n bits m = 0 (n = 0 to 65535) a m = 1 (n = 0 to 255) a l x = 0 s s + 1 y l m(s) s s + 1 y h m(s) x = 1 s s + 1 y l m(s) ply psh (note 17) m(s to s ?i + 1) a, b, x s s ?i i: number of bytes corresponding to register pushed on stack pul (notes 18 and 22) a, b, x m(s + 1 to s + i) s s + i i: number of bytes corresponding to register restored from stack plx x = 0 s s + 1 x l m(s) s s + 1 x h m(s) x = 1 s s + 1 x l m(s) rla (note 3) rmpa (note 19) m = 0 repeat (b, a) (b, a) + m(dt:x) ? m(dt:y) (signed) x x + 2 y y + 2 i i ?1 until i = 0 m = 1 repeat (b l , a l ) (b l , a l )+m(dt,x) m(dt,y) (signed) x x + 1 y y + 1 i i ?1 until i = 0 i: numder of repetitions (0 to 255) 16/8 16/8 16/8 16/8 16/8 16/8 31 5 3 07 + n
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-83 n z f5 4 1 a8 11 2 + 2i 1 + i 2 when the contents of ps is restored, this becomes the value. in the other cases, nothing changes. d5 4 1 n z nv zc 31 5 3 5a + 14 imm 67 13 2 + 3 i 1
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-84 rotate to the right by n bits (n = 0 to 31) e rotate to the right by n bits (n = 0 to 15) m = 0 a c b 15 ?b 0 m = 1 a l c b 7 ?b 0 rotate to the left by n bits (n = 0 to 31) e b 31 ?b 0 c rotate to the left by n bits (n = 0 to 15) m = 0 a b 15 ?b 0 c m = 1 a l b 7 ?b 0 c rotate to the right by 1 bit m = 0 acc or m16 c b 15 ?b 0 m = 1 acc l or m8 c b 7 ?b 0 rol (note 1) 21 7 3 1a 21 8 3 1b 21 7 3 3a 21 8 3 3b rotate to the left by 1 bit m = 0 acc or m16 b 15 ?b 0 c m = 1 acc l or m8 b 7 ?b 0 c ror (note 1) 13 1 1 81 2 2 13 53 1 1 81 2 2 53 rol #n (note 4) rold #n (note 4) ror #n (note 4) c1 6 2 60 + + imm imm d1 8 2 60 + + imm imm c1 6 2 20 + + imm imm rord #n (note 4) d1 8 2 20 + + imm imm 16/8 16/8 32 16/8 16/8 32 b 31 ?b 0 c
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-85 n zc n zc 21 7 4 1e 21 8 4 1f 21 7 4 3e 21 8 4 3f n zc n zc n zc n zc
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-86 acc acc ?m ?c 21 10 3 a9 a1 12 3 a9 s s + 1 ps l m(s) s s + 1 ps h m(s) s s + 1 pc l m(s) s s + 1 pc h m(s) s s + 1 pg m(s) rti f1 12 1 s s + 1 pc l m(s) s s + 1 pc h m(s) s s + 1 pg m(s) rtl 94 10 1 rtld n (notes 11 and 12) s s + 1 dprn l m(s) s s + 1 dprn h m(s) s s + 1 pc l m(s) s s + 1 pc h m(s) s s + 1 pg m(s). (n = 0 to 3. multiple dprs can be specified.) b1 3 3 a7 s s + 1 pc l m(s) s s + 1 pc h m(s) rts 84 7 1 sbc (notes 1 and 2) 31 3 3 a7 21 5 3 aa a1 7 3 aa 21 6 3 ab a1 8 3 ab 21 7 3 a0 a1 9 3 a0 21 8 3 a1 a1 10 3 a1 21 8 3 a8 a1 10 3 a8 21 9 3 a2 a1 11 3 a2 rtsd n (notes 11 and 12) sbcb (note 1) acc l acc l ?imm8 ?c b1 3 3 1b 31 3 3 1b s s + 1 dprn l m(s) s s + 1 dprn h m(s) s s + 1 pc l m(s) s s + 1 pc h m(s), (n = 0 to 3. multiple dprs can be specified.) 21 12 3 b9 c 1 sec 04 1 1 i 1 sei 05 4 1 sbcd e e ?m32 ?c 31 4 6 1d 21 7 3 ba 21 8 3 bb 21 9 3 b0 21 10 3 b1 21 10 3 b8 21 11 3 b2 16 16 16/8 8 32
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-87 value restored from stack 77 12 2 ?c + 3 i 77 15 2 ?c nv zc 21 5 4 ae a1 7 4 ae a1 8 4 af a1 8 4 a6 a1 9 5 ad a1 11 3 a4 a1 8 3 a3 a1 8 5 ac 21 6 4 af 21 6 4 a6 21 7 5 ad 21 6 5 ac 21 6 3 a3 21 9 3 a4 nv zc 77 11 2 ?8 + 3 i 77 14 2 ?8 1 1 nv zc 21 7 4 be 21 8 4 bf 21 8 4 b6 21 9 5 bd 21 8 5 bc 21 8 3 b3 21 11 3 b4
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-88 81 10 3 d9 d9 9 2 81 10 3 c9 c9 9 2 e9 11 2 91 9 3 39 11 9 3 39 m 1 sem 25 3 1 ps l (bit n) 1 (n = 0, 1, 3 to 7. multiple bits can be specified.) sep 99 3 2 m acc sta (note 1) da 4 2 81 5 3 da 81 6 3 db 11 7 3 d0 91 7 3 d0 11 8 3 d1 91 8 3 d1 d8 7 2 81 8 3 d8 11 9 3 d2 91 9 3 d2 stab (note 1) stad m8 acc l m32 e db 5 2 ca 4 2 81 5 3 ca 81 6 3 cb 11 7 3 c0 91 7 3 c0 11 8 3 c1 91 8 3 c1 c8 7 2 81 8 3 c8 11 9 3 c2 91 9 3 c2 cb 5 2 ea 6 2 11 9 3 e0 11 10 3 e1 e8 9 2 11 11 3 e2 eb 7 2 stp m x stx e2 4 2 41 6 3 f5 m y sty f2 4 2 41 6 3 fb 31 2 30 sub (notes 1 and 2) subb (note 1) acc acc ?m acc l acc l ?imm8 3a 3 2 81 4 3 3a 81 5 3 3b 11 6 3 30 91 6 3 30 11 7 3 31 91 7 3 31 11 7 3 38 91 7 3 38 11 8 3 32 91 8 3 32 3b 4 2 36 1 2 81 2 3 36 39 1 2 81 2 3 39 11 12 3 a9 subd subm (note 3) submb submd e e ?m32 m m ?imm m8 m8 ?imm8 m32 m32 ?imm32 aa 6 2 11 9 3 a0 11 10 3 a1 11 10 3 a8 11 11 3 a2 ab 7 2 3d 3 5 51 7 4 13 51 7 4 12 51 10 7 93 16/8 8 32 16/8 16/8 16/8 8 32 16/8 8 32 oscillation stopped
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-89 1 specified flag becomes ? (note 21) . 81 5 4 de 81 6 4 df 91 6 4 d6 81 6 5 dc 81 7 5 dd 11 6 3 d3 91 6 3 d3 11 9 3 d4 91 9 3 d4 de 4 3 df 5 3 11 6 4 d6 dc 5 4 dd 6 4 81 5 4 ce 81 6 4 cf 91 6 4 c6 81 6 5 cc 81 7 5 cd 11 6 3 c3 91 6 3 c3 11 9 3 c4 91 9 3 c4 ce 4 3 cf 5 3 11 6 4 c6 cc 5 4 cd 6 4 11 8 3 e3 11 11 3 e4 ee 6 3 ef 7 3 11 8 4 e6 ec 7 4 ed 8 4 e7 4 3 f7 4 3 nv zc 81 4 4 3e 81 5 4 3f 91 5 4 36 91 5 5 3c 91 6 5 3d 11 5 3 33 91 5 3 33 11 8 3 34 91 8 3 34 3e 3 3 3f 4 3 11 5 4 36 11 5 5 3c 11 6 5 3d nv zc nv zc 11 8 3 a3 11 11 3 a4 ae 6 3 af 7 3 11 8 4 a6 11 8 5 ac 11 9 5 ad nv zc nv zc nv zc 51 7 5 17 51 7 5 16 51 10 8 97
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-90 subs subx (note 4) s s ?imm8 x x ?imm (imm = 0 to 31) 31 2 3 0b suby (note 4) y y ?imm (imm = 0 to 31) 01 2 2 40 + imm 01 2 2 60 + imm dprn a (n = 0 to 3) tad n (note 20) s a tas s b dprn b (n = 0 to 3) x a tax y a x b y b a dprn (n = 0 to 3) tbs tbd n (note 20) tbx tby tda n (note 20) tay 31 3 2 n2 31 2 2 82 c4 1 1 d4 1 1 b1 3 2 n2 b1 2 2 82 81 2 2 c4 81 2 2 d4 b dprn (n = 0 to 3) tdb n (note 20) s dpr0 tds 31 2 2 73 b1 2 2 40 + n2 31 2 2 40 + n2 16 16/8 16/8 16 16 16/8 16/8 16 16 16/8 16/8 16/8 16/8 16
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-91 nv zc nv zc nv zc n z n z n z n z n z n z
l(dir), y function operation length (bit) addressing modes op n # imp imm a dir dir, x dir, y (dir) (dir, x) (dir), y symbol l(dir) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-92 a b a s b s x s tsa tsb tsx a x txa b x txb s x txs y x txy dpr0 s tsd 31 2 2 92 b1 2 2 92 31 4 2 70 31 2 2 f2 a4 1 1 81 2 2 a4 31 2 2 e2 31 2 2 c2 a y tya b y tyb x y tyx wit xab b4 1 1 81 2 2 b4 31 2 2 d2 31 2 10 55 2 1 16/8 16/8 16 16/8 16/8 16/8 16/8 16/8 16/8 16/8 16/8 16/8 cpu clock stopped
abs op n # op n # abs, x op n # abs, y op n # abl op n # abl, x op n # (abs) op n # l(abs) op n # (abs, x) op n # stk op n # rel op n # dir, b, r op n # abs, b, r op n # sr op n # (sr), y op n # blk op n # maa 10 9 8 7 6 5 4 3 2 1 0 ipl n v m x d i z c addressing modes processor status register appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-93 n z n z n z n z n z n z n z n z n z n z
appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-94 notes for machine instructions table the table lists the minimum number of instruction cycles for each instruction. the number of cycle is changed by the following condition. ?the value of the low-order bytes of dpr (dprn l ) the number of cycle of the addressing mode related with dprn (n = 0 to 3) is applied when dprn = 0. when dprn 0, add 1 to the number of cycles. ?the number of bytes of instruction which fetched into the instruction queue buffer ?the address at read and write of memory (either even or odd) ?when the external area accessed in byte = vcc level (at external data bus width 8 bits) ?the number of wait note 1. the op code at the upper row is used for accumulator a, and the op code at the lower row is used for accumulator b. note 2. w hen handing 16-bit data with flag m = 0 in the immediate addressing mode, add 1 to the numder of bytes. note 3. when handing 16-bit data with flag m = 0, add 1 to the numder of bytes. note 4. imm is the immediate value specified with an operand (imm = 0?1). note 5. the op code at the upper row is used for branching in the range of ?28 to +127, and the op code at the lower row is used for branching in the range of ?2768 to +32767. note 6. the brk instruction is a instruction for debugger; it cannot be used. note 7. any value from 0 through 15 is placed in an ?. note 8. when handling 16-bit data with flag x = 0 in the immediate addressing mode, add 1 to the numder of bytes. note 9. the number of cycles is the case of the 16-bit ?8-bit operation. in the case of the 32-bit 16-bit operation, add 8 to the number of cycles. note 10. when a zero division interrupt occurs, the number of cycles is 16 cycles. it is regardless of the data length. note 11. when placing a value in any of dprs, the op code at the upper row is applied. when placing values to multiple dprs, the op code at the lower row is applied. the letter ??represents the number of dprn specified: 1 to 4. note 12. a ??indicates to the value of 4 bits which the bit corressing to the specified dprn becomes ?. note 13. when the source is in the immediate addressing mode and flag m = 0, add n (n = 0 to 15) to the number of bytes. note 14. the number of cycles of the case of the 8-bit ? 8-bit operation. in the case of the 16-bit ? 16-bit operation, add 4 to the number of cycles.
appendix appendix 6. machine instructions 7906 group user? manual rev.2.0 20-95 note 15. the number of cycles is the case where the number of bytes to be transferred (i) is even. when the number of bytes to be transferred (i) is odd, the number is calculated as; 5 ? i + 10 note 16. the number of cycles is the case where the number of bytes to be transferred (i) is even. when the number of bytes to be transferred (i) is odd, the number is calculated as; 5 ? i + 14 note that it is 10 cycles in the case of 1-byte thanster. note 17. i 1 is the number of registers to be stored among a, b, x, y, dpr0, and ps. i 2 is the number of registers to be stored between dt and pg. note 18. letter ? 1 ?indicates the number of registers to be restored. note 19. the number of cycles is applied when flag m = ?.?when flag m=?,?the number is calculated as; 18 ? imm + 5 note 20. any value from 0 through 3 is placed in an ??in op code.
appendix appendix 7. countermeasure against noise 7906 group user? manual rev.2.0 20-96 ______ fig. 2 wiring for reset pin (2) wiring for clock input/output pins make the length of wiring connected to the clock input/output pins as short as possible. make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator, and the vss pin of the microcomputer, as short as possible (within 20 mm). separate the vss pattern for oscillation from all other vss patterns. (see figure 10.) reason: the microcomputer? operation synchronizes with a clock generated by the oscillation circuit. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a malfunction or a program runaway. also, if the noise causes a potential difference between the vss level of the microcomputer and the vss level of an oscillator, the correct clock will not be input in the microcomputer. appendix 7. countermeasure against noise general countermeasure examples against noise are described below. although the effect of these countermeasure depends on each system. the user shall modify them according to the actual application and test them. 1. short wiring length the wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. (1) ______ wiring for reset pin ______ make the length of wiring connected to the reset pin as short as possible. ______ in particular, connect a capacitor between the reset pin and the vss pin with the shortest possible wiring (within 20 mm). reason: ______ if noise is input to the reset pin, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. this may cause a program runaway. noise x in x out vss x in x out vss m37906 m37906 n o t a c c e p t a b l e a c c e p t a b l e fig. 3 wiring for clock input/output pins reset circuit vss reset vss m37906 a c c e p t a b l e reset reset circuit noise vss vss m37906 n o t a c c e p t a b l e
appendix appendix 7. countermeasure against noise 7906 group user s manual rev.2.0 20-97 (3) wiring for md0 and md1 pins connect md0 and md1 pins to the vss pin (or vcc pin) with the shortest possible wiring. reason: the processor mode of the microcomputer is influenced by a potential at the md0 and md1 pins when the md0 and md1 pins and the vss pin (or vcc pin) are connected. if the noise causes a potential difference between the md0 and md1 pins and the vss pin (or vcc pin), the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway. noise md0 vss m37906 vss m37906 a c c e p t a b l e n o t a c c e p t a b l e md1 md0 md1 fig. 4 wiring for md0 and md1 pins 2. connection of bypass capacitor between vss and vcc lines connect an approximate 0.1 f bypass capacitor as follows: connect a bypass capacitor between the vss and vcc pins, at equal lengths. the wiring connecting the bypass capacitor between the vss and vcc pins should be as short as possible. use thicker wiring for the vss and vcc lines than that for the other signal lines. fig. 5 bypass capacitor between vss and vcc lines bypass capacitor vcc vss m37906 wiring pattern wiring pattern
appendix appendix 7. countermeasure against noise 7906 group user s manual rev.2.0 20-98 3. wiring for analog input pins, analog power source pins, etc. (1) processing for analog input pins connect a resistor to the analog signal line, which is connected to an analog input pin, in series. additionally, connect the resistor to the microcomputer as close as possible. connect a capacitor between the analog input pin and the avss pin, as close to the avss pin as possible. reason: a signal which is input to the analog input pin is usually an output signal from a sensor. the sensor, which detects changes in status, is installed far from the microcomputer s printed circuit board. therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer s analog input pin. if a capacitor between an analog input pin and the avss pin is grounded far away from the avss pin, noise on the gnd line may enter the microcomputer through the capacitor. fig. 6 countermeasure example against noise for analog input pin using thermistor an i avss thermistor noise m37906 ri ci reference values ri : approximate 100 ? to 1000 ? ci : approximate 100 pf to 1000 pf notes 1: design an external circuit for the ani pin so that charge/discharge is available within 1 cycle of ad . 2: this resistor and thermistor are used to divide resistance. (note 2) a c c e p t a b l e a c c e p t a b l e n o t a c c e p t a b l e
appendix appendix 7. countermeasure against noise 7906 group user s manual rev.2.0 20-99 (2) processing for analog power source pins, etc. use independent power sources for the vcc, avcc and v ref pins. insert capacitors between the avcc and avss pins, and between the v ref and avss pins. reasons: prevents the a-d converter and d-a converter from noise on the vcc line. fig. 7 processing for analog power source pins, etc. avcc avss m37906 reference values c1 0.47 f c2 0.47 f note : connect capacitors using the thickest, shortest wiring possible. v ref an i c1 c2 (sensor, etc.)
appendix appendix 7. countermeasure against noise 7906 group user s manual rev.2.0 20-100 4. oscillator protection the oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) distance oscillator from signal lines with large current flows install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. reason: the microcomputer is used in systems which contain signal lines for controlling motors, leds, thermal heads, etc. noise occurs due to mutual inductance when a large current flows through the signal lines. (2) distance oscillator from signal lines with frequent potential level changes install an oscillator and its wiring pattern away from signal lines where potential levels change frequently. do not cross these signal lines over the clock-related or noise-sensitive signal lines. reason: signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. in particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. x in x out vss m m37906 mutual inductance large current x in x out v ss ? do not cross. m37906 ? i/o pin for signal with frequently changing potential levels fig. 9 wiring for signal lines where potential levels frequently change (3) oscillator protection using vss pattern print a vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. connect the vss pattern to the vss pin of the microcomputer with the shortest possible wiring, separating it from other vss patterns. x in x out vss an example of vss pattern on the underside of an oscillator. mounted pattern example of oscillator unit. separate vss lines for oscillation and supply. m37906 fig. 10 vss pattern underneath mounted oscillator fig. 8 wiring for signal lines where large current flows
appendix appendix 7. countermeasure against noise 7906 group user s manual rev.2.0 20-101 5. setup for i/o ports setup i/o ports by hardware and software as follows: connect a resistor of 100 ? or more to an i/o port in series. read the data of an input port several times to confirm that input levels are equal. since the output data may reverse because of noise, rewrite data to the output port s pi register periodically. rewrite data to port pi direction registers periodically. 6. reinforcement of the power source line for the vss and vcc lines, use thicker wiring than that of other signal lines. when using a multilayer printed circuit board, the vss and vcc patterns must each be one of the middle layers. the following is necessary for double-sided printed circuit boards: on one side, the microcomputer is installed at the center, and the vss line is looped or meshed around it. the vacant area is filled with the vss line. on the opposite side, the vcc line is wired the same as the vss line. noise direction register port latch data bus port fig. 11 setup for i/o ports
appendix appendix 8. 7906 group q & a 7906 group user? manual rev.2.0 20-102 appendix 8. 7906 group q & a information which may be helpful in fully utilizing the 7906 group is provided in q & a format. in q & a, as a rule, one question and its answer are summarized within one page. the upper box on each page is a question, and a box below the question is its answer. (if a question or an answer extends to two or more pages, there is a page number at the lower right corner.) at the upper right corner of each page, the main function related to the contents of description in that page is listed.
appendix 7906 group user? manual rev.2.0 20-103 appendix 8. 7906 group q & a interrupts q if an interrupt request (b) occurs while an interrupt routine (a) is executed, is it true that the main routine is not executed at all after the execution of the interrupt routine (a) is completed until the execution of the intack sequence for the next interrupt (b) starts? (2) if the next interrupt request (b) occurs immediately after sampling pulse ? is generated, the microcomputer executes one instruction of the main routine before executing the intack sequence for (b). it is because that the interrupt request is sampled by the next sampling pulse ? . an interrupt request is sampled by a sampling pulse generated synchronously with the cpu? op-code fetch cycle. (1) if the next interrupt request (b) occurs before sampling pulse ? for the rti instruction is gener- ated, the microcomputer executes the intack sequence for (b) without executing the main routine. (no instruction of the main routine is executed.) it is because that sampling is completed while executing the rti instruction. a conditions: flag i is cleared to ??by executing the rti instruction. the interrupt priority level of interrupt (b) is higher than ipl of the main routine. the interrupt priority detection time = 2 cycles of f sys . interrupt routine (a) main routine intack sequence for interrupt (b) sequence of execution rti instruction ? intack sequence for interrupt (b) interrupt request (b) interrupt routine (a) sampling pulse rti instruction ? main routine interrupt request (b) sampling pulse ? intack sequence for interrupt (b) one instruction executed ? interrupt routine (a) rti instruction
appendix appendix 8. 7906 group q & a 7906 group user s manual rev.2.0 20-104 interrupts suppose that there is a routine which should not accept a certain interrupt request. (this routine can accept any of the other interrupt request.) although the interrupt priority level select bits for a certain interrupt are set to 000 2 (in other words, although this interrupt is set to be disabled), this interrupt request is actually accepted immediately after the change of the priority level. why did this occur, and what should i do about it? as for the change of the interrupt priority level, if the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled: the next instruction (in the above example, it is the lda instruction) is already stored into a instruc- tion queue buffer of the biu. requirements for accepting the interrupt request which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. when writing to a memory or an i/o, the cpu passes an address and data to the biu. then, the cpu executes the next instruction in the instruction queue buffer while the biu is writing data into the actual address. detection of the interrupt priority level is performed at the beginning of each instruction. in the above case, the cpu executes the next instruction before the biu completes the change of the interrupt priority level. therefore, in the detection of the interrupt priority level performed synchronously with the execution of the next instruction, actually, the interrupt priority level before the change is used to detection, and its interrupt request is accepted. q a (1/2) interrupt request is accepted in this interval : movmb xxxic, #00h ; writes 000 2 to the interrupt priority level select bits. ; clears the interrupt request bit to 0. lda a,data ; instruction at the beginning of the routine which should not accept a certain interrupt request. :; previous instruction executed (instruction prefetched) cpu operation biu operation interrupt priority detection time sequence of execution writing to interrupt priority level select bits. change of interrupt priority level completed interrupt request accepted interrupt request generated movmb instruction executed lda instruction executed
appendix 7906 group user s manual rev.2.0 20-105 appendix 8. 7906 group q & a interrupts (2/2) a to prevent this problem, make sure that the routine which should not accept a certain interrupt request will be executed after the change of the interrupt priority level (ipl) has been completed. (this is to be made by software.) the following is a sample program. [sample program] after writing 000 2 to the interrupt priority level select bits, the instruction queue buffer is filled with several nop instructions to make the next instruction not to be executed before this writing is completed. : movmb xxxic, #00h ; writes 000 2 to the interrupt priority level select bits. nop ; inserts ten nop instructions. : nop ; lda a,data ; in struction at the beginning of the routine that should not accept a : certain interrupt request
appendix appendix 8. 7906 group q & a 7906 group user s manual rev.2.0 20-106 q after execution of the sei instruction, a branch is made in an interrupt routin. why did this occur? a sei ldab a, #00h cli interrupt routine rti sei ldab a, #00h cli interrupt routine rti interrupt request generated a when an interrupt request is generated before the sei instruction is executed, this interrupt request may be accepted immediately before the execution of the sei instruction. (this acceptance occurs depending on the timing when that interrupt request occurs.) in this case, a branch to the interrupt routine is made immediately after execution of the sei instruction. accordingly, the interrupt routine which is executed immediately after the sei instruction is due to an interrupt request generated before execution of the sei instruction. note that, in the routine ( a ) which should not accept the interrupt request, the following occur. (this routine follows the sei instruction.): no interrupt request is accepted. no branch to the interrupt routine is made. note: interrupt described here means maskable interrupt which can be disabled by the sei instruction. (refer to section ?.2 interruput source.? interrupts
appendix 7906 group user s manual rev.2.0 20-107 appendix 8. 7906 group q & a interrupts q (1) in both of the edge sense and level sense, an external interrupt request occurs when the input signal to the int i pin changes its level. this is independent of clock 1 . in the edge sense, also, the interrupt request bit is set to 1 at this time. (2) there are two methods: one uses external interrupt s level sense, and the other uses the timer s event counter mode. ? method using external interrupt? level sense as for hardware, input a logical sum of multiple interrupt signals (e.g., a , b , and c ) to the int i pin, and input each signal to each corresponding port pin. as for software, check the port pin s input levels in the int i interrupt routine in order to detect which signal ( a , b , or c ) was input. a (1) which timing of clock 1 is the external interrupts (input signals to the int i pin) detected? (2) when external interrupt input (int i ) pins are not enough, what should i do? ? method using timer? event counter mode as for hardware, input an interrupt signal to the tai in pin or tbi in pin. as for software, set the timer s operating mode to the event counter mode. then, set a value of 0000 16 into the timer register and select the valid edge. a timer s interrupt request occurs when an interrupt signal (selected valid edge) is input. a m37906 port pin port pin port pin int i b c
appendix appendix 8. 7906 group q & a 7906 group user s manual rev.2.0 20-108 watchdog timer in detection of a program runaway with usage of the watchdog timer, if the same value as that at the reset vector address is set to the watchdog timer interrupt s vector address, not performing software reset, how does it occur? when a branch is made to the branch destination address for reset within the watchdog timer interrupt routine, how does it occur? a the cpu registers and the sfr are not initialized in the above-mentioned way. accordingly, the user must initialize all of them by software. note that the processor interrupt priority level (ipl) retains 7 and is not initialized. consequently, all interrupt requests cannot be accepted. when rewriting the ipl by software, be sure to save the 16-bit immediate value to the stack area, and then restore that 16-bit immediate value to all bits of the processor status register (ps). when a program runaway occurs, we recommend to perform software reset in order to initialize the microcomputer. q
7906 group user? manual rev.2.0 20-109 appendix appendix 9. m37906m4c-xxxfp electrical characteristics appendix 9. m37906m4c-xxxfp electrical characteristics the electrical characteristics of the m37906m4c-xxxfp are described below. for the electrical characteristics, be sure to refer to the latest datasheets. unit v v v v v v ma ma ma ma ma ma mhz mhz max. 5.5 vcc 0.2 v cc ?0 ? 10 20 5 15 20 20 parameter power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 low-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 high-level peak output current p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 high-level average output current p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 low-level peak output current p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p7 0 ?7 4 low-level peak output current p6 0 ?6 5 low-level average output current p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p7 0 ?7 4 low-level average output current p6 0 ?6 5 external clock input frequency (note 1) system clock frequency symbol v cc av cc v ss av ss v ih v il i oh(peak) i oh(avg ) i ol(peak) i ol(peak) i ol(avg) i ol(avg) f(x in ) f(f sys ) parameter power source voltage analog power source voltage input voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , v cont , v ref , x in , reset, byte, md0, md1 output voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , x out power dissipation operating ambient temperature storage temerature symbol v cc av cc v i v o p d t opr t stg absolute maximum ratings recommended operating conditions (vcc = 5 v, ta = ?0 to 85 ?, unless otherwise noted) notes 1: when using the pll frequency multiplier, be sure that f(f sys ) = 20 mhz or less. 2: the average output current is the average value of an interval of 100 ms. 3: the sum of i ol(peak) must be 110 ma or less, the sum of i oh(peak) must be 80 ma or less. unit v v v v mw ? ? ratings ?.3 to 6.5 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to v cc +0.3 300 ?0 to 85 ?0 to 150 limits min. 4.5 0.8 vcc 0 typ. 5.0 v cc 0 0
appendix 7906 group user? manual rev.2.0 20-110 appendix 9. m37906m4c-xxxfp electrical characteristics output-only pins are open, and the other pins are con- nected to vss or vcc. an external square-waveform clock is input. (pin x out is open.) the pll frequency multiplier is inactive. unit v v v v v a a v ma a f(f sys ) = 20 mhz. cpu is active. ta = 25 c when clock is inactive. ta = 85 c when clock is inactive. test conditions i oh = ?0 ma i ol = 10 ma v i = 5.0 v v i = 0 v when clock is inactive. parameter high-level output voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 low-level output voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 hysteresis ta0 in ?a2 in , ta4 in , ta9 in , ta0 out ?a2 out , ta4 out , ta9 out , tb0 in ?b2 in , int 3 ?nt 7 , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 , rtp trg0 , p6out cut hysteresis reset hysteresis x in high-level input current p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 low-level input current p1 0 ?1 7 , p2 0 ?2 7 , p5 0 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 ram hold voltage power source current symbol v oh v ol v t+ vt v t+ vt v t+ vt i ih i il v ram i cc dc electrical characteristics (vcc = 5 v, vss = 0 v, ta = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) min. 3 0.4 0.5 0.1 2 limits typ. 25 max. 2 1 1.5 0.3 5 ? 50 1 20
7906 group user? manual rev.2.0 20-111 appendix appendix 9. m37906m4c-xxxfp electrical characteristics resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(f sys ) 20 mhz max. a-d converter characteristics (v cc = av cc = 5 v ?0.5 v, v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode comparater 10-bit resolution mode 8-bit resolution mode comparater 5 5.9 2.45 (note) 0.7 (note) 2.7 0 10 ?3 ?2 ?40 v cc v ref bits v lsb lsb mv k ? s v v note: this is applied when a-d conversion freguency ( ad ) = f 1 ( ). d-a converter characteristics (v cc = 5 v, v ss = av ss = 0 v, v ref = 5 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol limits typ. min. max. test conditions resolution absolute accuracy set time output resistance reference power source input current t su r o i vref (note) 2 3.5 8 ?1.0 3 4.5 3.2 bits % s k ? ma note: the test conditions are as follows: ?one d-a converter is used. ?the d-a register value of the unused d-a converter is ?0 16 . ?the reference power source input current for the ladder resistance of the a-d converter is excluded. s reset input low-level pulse width t w(resetl) symbol parameter min. limits unit reset input reset input timing requirements (v cc = 5 v ?0.5 v, v ss = 0v, ta = ?0 to 85 ?, unless otherwise noted) 10 max. typ. reset input t w(resetl) a-d converter comparator 256 1 v ref typ.
appendix 7906 group user? manual rev.2.0 20-112 appendix 9. m37906m4c-xxxfp electrical characteristics t c(ta) t w(tah) t w(tal) f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz peripheral device input/output timing (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) ? for limits depending on f(f sys ), their calculation formulas are shown below. also, the values at f(f sys ) = 20 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol taj out input cycle time taj out input high-level pulse width taj out input low-level pulse width taj out input setup time taj out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol taj in input high-level pulse width taj in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(f sys ) (400) taj in input cycle time taj in input high-level pulse width taj in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(ta) t w(tah) t w(tal) taj in input cycle time taj in input high-level pulse width taj in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the taj in input cycle time requires 4 or more cycles of a count source. the taj in input high-level pulse width and the taj in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol taj in input cycle time taj in input high-level pulse width taj in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(f sys ) 20 mhz
7906 group user? manual rev.2.0 20-113 appendix appendix 9. m37906m4c-xxxfp electrical characteristics t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) (p = 2, 4, 9) tap in input cycle time tap in input setup time tap out input setup time t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(up-t in ) t su(tap in -tap out ) t su(tap out -tap in ) t su(tap in -tap out ) t su(tap out -tap in ) t c(ta) ?gating input in timer mode ?count input in event counter mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode taj in input taj out input (up-down input) taj out input (up-down input) ?up-down and count input in event counter mode taj in input (when count by falling) taj in input (when count by rising) tap in input tap out input ?two-phase pulse input in event counter mode test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il = 1.0 v, v ih = 4.0 v
appendix 7906 group user? manual rev.2.0 20-114 appendix 9. m37906m4c-xxxfp electrical characteristics f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit
7906 group user? manual rev.2.0 20-115 appendix appendix 9. m37906m4c-xxxfp electrical characteristics t w(inh) t w(inl) symbol int i input high-level pulse width int i input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input t c(tb) t w(tbh) t w(tbl) t su(d-c) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c-q) t h(c-d) t h(c-q) tbi in input int i input clk i input txd i output rxd i input test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 1.0 v, v ih = 4.0 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf
appendix 7906 group user? manual rev.2.0 20-116 appendix 9. m37906m4c-xxxfp electrical characteristics t c t w(half) t w(h) t w(l) t r t f max. 0.55 tc 8 8 min. 50 0.45 tc 0.5 t c ?8 0.5 t c ?8 external clock input cycle time external clock input pulse width with half input-voltage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time limits external clock input symbol parameter ns ns ns ns ns ns unit external clock input t r t f t w(l) t w(h) t w(half) f(x in ) t c test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 1.0 v, v ih = 4.0 v (t w(h) , t w(l) , t r , t f ) input timing voltage : 2.5 v ( t c , t w(half) ) timing requirements (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted)
appendix 7906 group user? manual rev.2.0 20-117 appendix 10. m37906m4c-xxxfp standard characteristics appendix 10. m37906m4c-xxxfp standard characteristics standard characteristics described below are just examples of the m37906m4c-xxxfp? characteristics and are not guaranteed. for each parameter? limits, refer to sections ?ppendix 9. m37906m4c-xxxfp electrical characteristics. 1. programmable i/o port (cmos output) standard characteristics: p1, p2, p5, p7 (1) p-channel i oh ? oh characteristics power source voltage: vcc = 5 v (2) n-channel i ol ? ol characteristics power source voltage: vcc = 5 v 5.0 0 v oh [v] i oh [ma] 4.0 3.0 2.0 1. 0 15.0 30.0 ta=25 c ta=85 c 5. 0 i ol [ma] v ol [v] 0 4.0 3.0 2.0 1. 0 15.0 30.0 ta=25 c ta=85 c
appendix appendix 10. m37906m4c-xxxfp standard characteristics 7906 group user s manual rev.2.0 20-118 2. programmable i/o port (cmos output) standard characteristics: p6 (1) p-channel i oh ? oh characteristics power source voltage: vcc = 5 v (2) n-channel i ol ? ol characteristics power source voltage: vcc = 5 v v oh [v] i oh [ma] 4.0 3.0 2.0 1.0 15.0 30.0 0 5. 0 ta=25 c ta=85 c v ol [v] i ol [ma] 4.0 3.0 2.0 1.0 15.0 30.0 0 5. 0 ta=25 c ta=85 c
appendix 7906 group user s manual rev.2.0 20-119 appendix 10. m37906m4c-xxxfp standard characteristics 3. icc?(x in ) standard characteristics measurement condition vcc = 5.0 v ta = 25 c f(x in ) : square waveform input single-chip mode pll frequency multiplier is inactive. external clock input select bit = 1 30 icc [ma] f(x in ) [mhz ] 25 20 15 10 5 0 5.0 25.0 10.0 15.0 20.0 0.0 30.0 35.0 at wait mode active at reset (pll frequency multiplier is active.)
appendix appendix 10. m37906m4c-xxxfp standard characteristics 7906 group user s manual rev.2.0 20-120 4. a-d converter standard characteristics the lower lines of the graph indicate the absolute precision errors. these are expressed as the deviation from the ideal value when the output code changes. for example, the change in m37906m4c-xxxfp s output code from 159 to 160 should occur at 797.5 mv, but the measured value is +2.75 mv. accordingly, the measured point of change is 797.5 + 2.75 = 800.25 mv. the upper lines of the graph indicate the input voltage width for which the output code is constant. for example, the measured input voltage width for which the output code is 56 is 6.0 mv, so that the differential non-linear error is 6.0 5 = 1.0 mv (0.20 lsb).
appendix 7906 group user s manual rev.2.0 20-121 appendix 10. m37906m4c-xxxfp standard characteristics (measurement conditions vcc = 5.0 v, v ref = 5.12 v, f(f sys ) = 20 mhz, ta = 25 c, ad = f(f sys ) divided by 2)
appendix appendix 11. memory assignment of 7906 group 7906 group user? manual rev.2.0 20-122 appendix 11. memory assignment of 7906 group 1. m37906f8, m37906m8 fig. 12 memory assigments of m37906f8, m37906m8 2. m37906m6 m37906m8 0 16 ff 16 100 16 3ff 16 400 16 fff 16 1000 16 ffff 16 0 16 ff 16 100 16 3ff 16 400 16 fff 16 1000 16 ffff 16 sfr area sfr area unused area unused area bank 0 16 bank 0 16 m37906f8 internal ram area (3 kbytes) internal flash memory area (user rom area) (60 kbytes) internal rom area (60 kbytes) internal ram area (3 kbytes) note: do not assign a program to the last 8 bytes of the internal ram area. bank 0 16 unused area unused area 0 16 ff 16 100 16 3ff 16 400 16 fff 16 1000 16 3fff 16 4000 16 ffff 16 internal rom area (48 kbytes) internal ram area (3 kbytes) (note) sfr area m37906m6 fig. 13 memory assigment of m37906m6
appendix 7906 group user s manual rev.2.0 20-123 appendix 11. memory assignment of 7906 group fig. 14 memory assigment of m37906m4 3. m37906m4 ffff 16 7fff 16 8000 16 fff 16 1000 16 bff 16 c00 16 0 16 ff 16 100 16 m37906m4 sfr area unused area unused area internal ram area (1 kbyte) (note) bank 0 16 note: do not assign a program to the last 8 bytes of the internal ram area. internal rom area (32 kbytes)
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mitsubishi semiconductors user? manual 7906 group rev.2.0 dec. 20, 2001 editioned by committee of editing of mitsubishi semiconductor user? manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?001 mitsubishi electric corporation
user? manual 7906 group new publication, effective dec. 2001. specifications subject to change without notice. ?2001 mitsubishi electric corporation.

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